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rev. 1.0 8/10 copyright ? 2010 by silicon laborato ries cp2400/1/2/3 cp2400/1/2/3 128/64 s egment lcd d river lcd driver ?? controls up to 128 segments (48-pin packages) or 64 segments (32-pin package) ?? supports static, 2-mux, 3-mux, and 4-mux displays ?? on-chip bias generation with internal charge pump ?? low power blink capability gpio expander ?? expands gpio count by up to 36 pins (48-pin packages) or 20 pins (32-pin package) ?? gpio pins may be configured to push-pull or open-drain outputs with two drive levels. gpio may also be used as digital inputs (cp2400/1/2/3 pullups included) ?? port match capability can wa ke up host controller using interrupt pin ?? 5 v tolerant i/o real time clock, smartclock ?? precision time keeping with 32.768 khz watch crystal; self-oscillate mode requires no external crystal; accepts external 32 khz cmos clock ?? 36-hour programmable counter with wake up alarm ?? can wake up the host controller using interrupt pin ?? low power (<1.5 a) 256 bytes ram ?? general purpose ram expands the memory available to host controller. 16-bit timers ?? two general purpose 16-bit timers clock sources ?? 20 mhz internal oscillator ?? can be clocked from an external cmos clock digital bus interface ?? 4-wire spi interface operates up to 2.5 mbps with synchronous external clock or up to 1 mbps with internal clock (cp2400/2 only). ?? 2-wire smbus/i 2 c interface operates up to 400 khz with internal clock (cp2401/3 only). ?? dedicated rst and int pins. ?? optional clk pin can be used as a cmos clock input. ?? optional pwr pin (smbus/i 2 c devices only) places the device in a low power mode. spi devices use the nss pin to place the device in a low power mode. low power ?? 1.8?3.6 v operation wit h integrated ldo ?? ultra low power mode w/ lcd (<3 a typical) ?? shutdown current (0.05 a typical) example applications ?? handheld equipment ?? utility meters ?? thermostat display ?? home security systems packages ?? pb-free 48-pin qfp (9x9 mm footprint) [-q] ?? pb-free 48-pin qfn (7 x7 mm footprint) [-m] ?? pb-free 32-pin qf n (5x5 mm footprint) ordering part numbers ?? cp2400-g[m|q] (spi interface) ?? cp2401-g[m|q] (smbus/i 2 c interface) ?? CP2402-gm (spi interface) ?? cp2403-gm (smbus/i 2 c interface) temperature range: ?40 to +85 c host interface spi (cp2400/2) or smbus/i2c (cp2401/3) 20 mhz internal oscillator 256 byte sram 2 x 16-bit timers gpio expander smartclock 32.768 khz cp2400/1/2/3 host controller digital i/o optional lcd controller lcd www.datasheet.in
cp2400/1/2/3 2 rev. 1.0 www.datasheet.in
cp2400/1/2/3 rev. 1.0 3 1. system overview ............ ................ ................. ................ ................. ................ ................ ...5 1.1. typical connection diagram ................. ................ ................. .............. .............. ............9 2. absolute maximum ratings.............. .............. .............. .............. .............. .............. .......... 11 3. electrical characteristics . ................. ................ ................ ................. ................ ............... 1 2 4. pinout and package definitions ....... .............. .............. .............. .............. .............. .......... 17 5. clocking options ............ ................ ................. ................ ................. ................ ............... ..32 6. internal registers and me mory ................... ................. .............. .............. .............. .......... 34 6.1. accessing internal registers and ram over the spi interface ... .............. ........... ........ 35 6.2. accessing internal register s and ram over the smbus interf ace ............... ............... 36 6.3. internal registers ........ ................. ................ ................ ................. ................ ............... 37 7. interrupt sources ............ ................ ................. ................ ................. ................ .............. ...40 8. reset sources ............... ................ ................ ................. ................ ................. ............... .... 47 8.1. reset initialization ..... ................ ................. ................ ................. ................ ................ .47 8.2. power-on reset............. ................ ................ ................. ................ ................. ............ 48 8.3. external pin reset....... ................. ................ ................ ................. ................ ...............4 8 9. power modes............ ................ ................. .............. .............. .............. .............. ............. ....49 9.1. normal mode........ ................. ................ ................ .............. ............... .............. ............ 50 9.2. ram preservation mode .. ................ ................. ................ ................. ................ .......... 50 9.3. ultra low power lcd mode......... .............. .............. .............. .............. .............. .......... 51 9.4. ultra low power smartc lock mode............. ................. ................ ................. ............ 52 9.5. shutdown mode ............. ................ ................ ................. ................ ................. ............ 53 9.6. determining the ulp m ode wake-up source.......... .............. .............. .............. ..........55 9.7. port match functionality in the ultra low powe r modes...................... .............. .......... 56 9.8. disabling secondary device functi ons................. ................. .............. .............. .......... 58 10. port input/output ............ ................ ................. ................ ................. ................ ............. ....60 10.1.port i/o modes of operation ..... ................. .............. .............. .............. .............. .......... 61 10.2.assigning port i/o pins to a nalog and digital functions ............ .............. ........... ........ 62 10.3.active mode port match. ................ ................ ................. ................ ................. ............ 63 10.4.registers for accessing and configuring port i/o ................. .............. .............. ..........65 11. smartclock (real time cl ock)................... ................. .............. .............. .............. .......... 69 11.1.smartclock interface..... ................ ................. ................ ................. ................ ..........70 11.2.smartclock clocking sources..... ................ ................. ................ ................. ............74 11.3.smartclock timer and alarm func tion ............ ................ ................. .............. ..........77 12. lcd segment driver ......... ................. ................ ................ ................. ................ ............... 83 12.1.initializing the lc d segment driver ...... ................ ................. .............. .............. .......... 83 12.2.lcd configuration ......... ................ ................ ................. ................ ................. ............ 84 12.3.lcd bias generat ion and contrast adjustment ............... ................. ................ .......... 85 12.4.lcd timing generation ..... ................. ................ ................ ................. .............. .......... 87 12.5.mapping ulp memory to lcd pins ............. .............. .............. .............. .............. ........ 90 12.6.blinking lcd segmen ts ...................... ................ ................ ................. .............. .......... 91 13. timers ................ ................ ................. .............. .............. .............. .............. ............. ........... 92 13.1.timer 0 ............. ................ ................. .............. .............. .............. .............. ............. .... 92 13.2.timer 1 ............. ................ ................. .............. .............. .............. .............. ............. .... 96 14. serial peripheral interface (spi) .................. .............. .............. ............... .............. .......... 101 14.1.signal descriptions ........ ................ ................ ................. ................ ................. .......... 101 14.2.serial clock timing ................... .............. .............. .............. ............... .............. .......... 102 www.datasheet.in
cp2400/1/2/3 4 rev. 1.0 15. smbus interface.............. ................ ................. ................ ................. ................ ............. .. 104 15.1.supporting documents . ................... ................. ................ ................. .............. .......... 104 15.2.smbus configuration ..... ................ ................ ................. ................ ................. .......... 104 15.3.smbus operation.... ................ ................ .............. .............. ............... .............. .......... 105 document change list ....... ................ .............. .............. .............. ............... .............. .......... 10 8 contact information .......... ................ ................ ................. ................ ................. ............... ..110 www.datasheet.in
cp2400/1/2/3 rev. 1.0 5 1. system overview cp2400/1/2/3 devices are fixed function lcd drivers that can also be used for expanding gpio, timekeeping, and increasing available system ram by up to 256 bytes. t he device is controlled using di rect and indirect internal registers accessible through the 4-wire spi or 2-wire sm bus interface. all digital pins on the device are 5 v tolerant. figure 1.1. cp2400 block diagram port 0 drivers gpio expander p0.0/lcd0 p0.1/lcd1 p0.2/lcd2 p0.3/lcd3 p0.4/lcd4 p0.5/lcd5 p0.6/lcd6 p0.7/lcd7 port i/o configuration sfr bus port 1 drivers p1.0/lcd8 p1.1/lcd9 p1.2/lcd10 p1.3/lcd11 p1.4/lcd12 p1.5/lcd13 port 2 drivers p2.0/lcd16 p2.1/lcd17 p2.2/lcd18 p2.3/lcd19 p2.4/lcd20 system clock configuration external cmos clock low power 20 mhz oscillator p1.6/lcd14 p1.7/lcd15 p2.5/lcd21 p2.6/lcd22 p2.7/lcd23 smartclock oscillator xtal1 xtal2 host interface port 3 drivers p3.0/lcd24 p3.1/lcd25 p3.2/lcd26 p3.3/lcd27 p3.4/lcd28 p3.5/lcd29 p3.6/lcd30 p3.7/lcd31 port 4 drivers p4.0/com0 p4.1/com1 p4.2/com2 p4.3/com3 clk sysclk 2 x timer (16-bit) 256 byte sram int mosi miso sck power net vdd power on reset reset rst gnd vreg digital power analog power spi (4-wire) lcd control charge pump segment ram mux decode logic cap power management nss www.datasheet.in
cp2400/1/2/3 6 rev. 1.0 figure 1.2. cp2401 block diagram port 0 drivers gpio expander p0.0/lcd0 p0.1/lcd1 p0.2/lcd2 p0.3/lcd3 p0.4/lcd4 p0.5/lcd5 p0.6/lcd6 p0.7/lcd7 port i/o configuration sfr bus port 1 drivers p1.0/lcd8 p1.1/lcd9 p1.2/lcd10 p1.3/lcd11 p1.4/lcd12 p1.5/lcd13 port 2 drivers p2.0/lcd16 p2.1/lcd17 p2.2/lcd18 p2.3/lcd19 p2.4/lcd20 system clock configuration external cmos clock low power 20 mhz oscillator p1.6/lcd14 p1.7/lcd15 p2.5/lcd21 p2.6/lcd22 p2.7/lcd23 smartclock oscillator xtal1 xtal2 host interface port 3 drivers p3.0/lcd24 p3.1/lcd25 p3.2/lcd26 p3.3/lcd27 p3.4/lcd28 p3.5/lcd29 p3.6/lcd30 p3.7/lcd31 port 4 drivers p4.0/com0 p4.1/com1 p4.2/com2 p4.3/com3 clk sysclk 2 x timer (16-bit) 256 byte sram int scl sda smba0 power net vdd power on reset reset rst gnd vreg digital power analog power smbus/i2c (2-wire) lcd control charge pump segment ram mux decode logic cap pwr power management www.datasheet.in
cp2400/1/2/3 rev. 1.0 7 figure 1.3. CP2402 block diagram port 0 drivers gpio expander p0.0/lcd0 p0.1/lcd1 p0.2/lcd2 p0.3/lcd3 p0.4/lcd4 p0.5/lcd5 p0.6/lcd6 p0.7/lcd7 port i/o configuration sfr bus port 1 drivers p1.0/lcd8 p1.1/lcd9 p1.2/lcd10 p1.3/lcd11 p1.4/lcd12 p1.5/lcd13 system clock configuration external cmos clock low power 20 mhz oscillator p1.6/lcd14 p1.7/lcd15 smartclock oscillator xtal1 xtal2 host interface port 2 drivers p2.0/com0 p2.1/com1 p2.2/com2 p2.3/com3 clk sysclk 2 x timer (16-bit) 256 byte sram int mosi miso sck power net vdd power on reset reset rst gnd vreg digital power analog power spi (4-wire) lcd control charge pump segment ram mux decode logic cap power management nss www.datasheet.in
cp2400/1/2/3 8 rev. 1.0 figure 1.4. cp2403 block diagram port 0 drivers gpio expander p0.0/lcd0 p0.1/lcd1 p0.2/lcd2 p0.3/lcd3 p0.4/lcd4 p0.5/lcd5 p0.6/lcd6 p0.7/lcd7 port i/o configuration sfr bus port 1 drivers p1.0/lcd8 p1.1/lcd9 p1.2/lcd10 p1.3/lcd11 p1.4/lcd12 p1.5/lcd13 system clock configuration external cmos clock low power 20 mhz oscillator p1.6/lcd14 p1.7/lcd15 smartclock oscillator xtal1 xtal2 host interface port 2 drivers p2.0/com0 p2.1/com1 p2.2/com2 p2.3/com3 clk sysclk 2 x timer (16-bit) 256 byte sram int scl sda smba1 power net vdd power on reset reset rst gnd vreg digital power analog power smbus/i2c (2-wire) lcd control charge pump segment ram mux decode logic cap pwr power management smba0 www.datasheet.in
cp2400/1/2/3 rev. 1.0 9 1.1. typical connection diagram figure 1.5. typical connection diagram (spi interface) cp240x xtal2 xtal1 32.768 khz vdd vdd 0.1 uf mcu sck sck miso miso rst lcd gnd gnd mosi mosi lcd0 lcdn com1 com3 com4 com2 com0 com2 com3 com1 segment pin 1 segment pin (n+1) gpio clk gpio cap 10 uf int gpio nss nss px.x px.y gpio, analog, etc. www.datasheet.in
cp2400/1/2/3 10 rev. 1.0 figure 1.6. typical connection diagram (smbus/i 2 c interface) cp240x xtal2 xtal1 32.768 khz vdd vdd 0.1 uf mcu scl scl sda sda rst lcd gnd gnd lcd0 lcdn com1 com3 com4 com2 com0 com2 com3 com1 segment pin 1 segment pin (n+1) gpio clk gpio cap 10 uf int gpio gpio pwr px.x px.y gpio, analog, etc. smba0 vdd www.datasheet.in
cp2400/1/2/3 rev. 1.0 11 2. absolute maximum ratings table 2.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any i/o pin or rst with respect to gnd v dd > 2.2 v v dd < 2.2 v ?0.3 ? 5.8 v dd + 3.6 v voltage on v dd with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd and gnd ? ? 500 ma maximum output current sunk by rst or any i/o pin ? ? 100 ma note: stresses above those listed may cause permanent damage to t he device. this is a stress rating only, and functional operation of the devices at or exceeding the conditions in th e operation listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. www.datasheet.in
cp2400/1/2/3 12 rev. 1.0 3. electrical characteristics table 3.1. global electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units supply voltage 1.8 3.3 3.6 v sysclk 0 ? 25 mhz t sysh (sysclk high time) 18 ? ? ns t sysl (sysclk low time) 18 ? ? ns specified operating tem perature range ?40 ? +85 c normal mode supply current (v dd = 3.0 v, 25 c unless otherwise specified) 20 mhz internal oscillator divided by 1, sysclk = 20 mhz, spi data rate = 1 mbps * v dd =3.6v v dd =3.0v v dd =1.8v ? ? ? 740 700 630 790 ? ? a accessing ram at 1 mbps ? 740 ? a sysclk = 10 mhz, spi data rate * = 500 kbps ? 380 ? a sysclk = 5 mhz, spi data rate * = 250 kbps ? 230 ? a sysclk = 2.5 mhz, spi data rate * = 125 kbps ? 150 ? a ram preservation mode supply current (v dd = 3.0 v, 25 c unless otherwise specified) 32.768 khz smartclock selected as the system clock, internal oscillator disabled ?20?a ultra low power lcd mode supply current (v dd = 3.0 v, 25 c unless otherwise specified) lcd enabled with charge pump enabled, 60 hz refresh rate, no load smartclock with 32.768 khz crystal 4-mux mode 3-mux mode 2-mux mode static mode ? ? ? ? 2.3 2.3 2.2 2.1 ? ? ? ? a lcd enabled with charge pump enabled, 60 hz refresh rate, no load smartclock in self-o scillate mode (agc enabled, loadcap = 0x0f) 4-mux mode 3-mux mode 2-mux mode static mode ? ? ? ? 1.7 1.7 1.7 1.5 ? ? ? ? a ultra low power smartclock mode supply current (v dd = 3.0 v, 25 c unless otherwise specified) external crystal (rtc timer enabled) fosc = 32.768 khz ? 2.5 ? a cmos clock input on xtal1 and xtal2 pins (rtc timer enabled) fosc = 32.768 khz ? 2.3 ? a self-oscillate mode (agc enabled, loadcap = 0x0f) (rtc timer enabled) fosc = 14 khz ? 2.0 ? a shutdown mode (v dd = 3.0 v, 25 c unless otherwise specified) shutdown (no clocks active, regulator disabled) v dd =3.6v v dd =3.0v v dd =1.8v ? ? ? 0.030 0.020 0.015 ? ? ? a *note: indicates maximum allowed spi data rate in this mode. power measurement taken with no spi traffic. www.datasheet.in
cp2400/1/2/3 rev. 1.0 13 table 3.2. port i/o dc electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage high driv e strength, pndrv.n = 1 i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull low drive strength, pndrv.n = 0 i oh = ?1 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?3 ma, port i/o push-pull v dd ?0.7 v dd ?0.1 ? v dd ?0.7 v dd ?0.1 ? ? ? see chart ? ? see chart ? ? ? ? ? ? v output low voltage high drive strength, pndrv.n = 1 i ol = 8.5 ma i ol = 10 a i ol = 15 ma low drive strength, pndrv.n = 0 i ol = 1.4 ma i ol = 10 a i ol = 4 ma ? ? ? ? ? ? ? ? see chart ? ? see chart 0.6 0.1 ? 0.6 0.1 ? v input high voltage v dd = 2.0 to 3.6 v v dd ? 0.6 ??v v dd = 1.8 to 2.0 v 0.7 x v dd ??v input low voltage v dd = 2.0 to 3.6 v ? ? 0.6 v v dd = 1.8 to 2.0 v ?? 0.3 x v dd v input leakage current weak pullup on, v in = 0 v, v dd = 1.8 v weak pullup on, vin = 0 v, v dd = 3.6 v ? ? 4 20 ? 30 a www.datasheet.in
cp2400/1/2/3 14 rev. 1.0 figure 3.1. typical voh typical voh (high drive mode) 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 0 5 10 15 20 25 30 35 40 45 50 load current (ma) voltag e vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v typical voh (low drive mode) 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 0123456789101112131415 load current (ma) voltag e vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v www.datasheet.in
cp2400/1/2/3 rev. 1.0 15 figure 3.2. typical vol typical vol (high drive mode) 0 0.3 0.6 0.9 1.2 1.5 1.8 -80 -70 -60 -50 -40 -30 -20 -10 0 10 load current (ma) voltag e vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v typical vol (low drive mode) 0 0.3 0.6 0.9 1.2 1.5 1.8 -10-9-8-7-6-5-4-3-2-1 0 load current (ma) voltag e vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v www.datasheet.in
cp2400/1/2/3 16 rev. 1.0 table 3.3. reset electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units rst input high voltage 0.7 x v dd ??v rst input low voltage ? ? 0.3 x v dd v rst input pullup current rst = 0 v, v dd = 1.8 v rst = 0 v, v dd = 3.6 v ? ? 4 20 ? 30 a v dd ramp time for power on 1 v dd ramp from 0?1.8 v ?? 1ms power on reset delay (t pordelay ) from start of ramp until the reset complete interrupt v dd = 1.8 v v dd = 3.0 v v dd = 3.6 v ? ? ? 1200 660 575 ? 900 ? s required rst low time to guarantee a system reset (t rst ) see note 2 15 ? ? s startup delay from reset de- asserted until the reset complete interrupt (t startup ) pin reset ? 90 100 s notes: 1. there is no restriction on vdd ramp time if the rst pin is toggled at the end of the ramp. 2. if the rst pin is held low for a shorter time period, a device reset may occur. table 3.4. power management electrical specifications v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units ram preservation mode wake-up time from the falling edge of clk until host interface ready 10 ns ulp mode wake-up time (from the falling edge of nss/pwr to the reset comple te interrupt) port match or smartclock wakeup nss/pwr pin wakeup 3 7 ? ? 4 8 rtc cycles table 3.5. internal oscillator electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specified; using factory-calibrated settings. parameter conditions min typ max units oscillator frequency ?40 to +85 c, v dd = 1.8?3.6 v 15 20 25 mhz oscillator supply current (from v dd ) 25 c ? 50 ? a table 3.6. lcd electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specified. parameter conditions min typ max units charge pump output voltage error ? 30 ? mv www.datasheet.in
cp2400/1/2/3 rev. 1.0 17 4. pinout and package definitions table 1. cp2400/1/2/3 pin definitions name pin numbers type description 48-pin 32-pin spi i 2 c spi i 2 c xtal1 1 1 1 1 a in crystal input. this pin is the return for the external oscillator driver. this pin can be overdriven by an external cmos clock. xtal2 2 2 2 2 a out crystal output. this pin is the excitation driver for a quartz crystal. v dd 3 3 3 3 power in 1.8?3.6 v power supply voltage input. gnd 4 4 4 4 ground cap 48483232power out lcd power supply voltage output. this pin requires a 10 f decoupling capacitor. clk 47 47 31 31 d in cmos clock input. this pin should not be left floating. rst 46 46 30 30 d in device reset. an external source can initiate a system reset by driving this pin low for at least 15 s. this pin has an internal weak pullup. int 45 45 29 29 d out interrupt serv ice request. this pin prov ides notification to the host. this pin is a push-pull output. nss 44 ? 28 ? d in slave select signal for spi interface. this pin should not be left floating. mosi 43 ? 27 ? d in master out/slave in data signal for spi interface. this pin should not be left floating. miso 42 ? 26 ? d out master in/slave ou t data signal for spi interface sck 41 ? 25 ? d in clock signal for spi interface. this pin should not be left floating. pwr ? 44 ? 28 d in allows smbus device to enter the ultra low power mode. this pin should not be left floating. scl ? 43 ? 27 d i/o clock signal for smbus interface. this pin should not be left floating. sda ? 42 ? 26 d i/o data signal for smbus interface. this pin should not be left floating. smba0 ? 41 ? 25 d in bit 0, smbus slave address. this pin should not be left floating. p0.0 lcd0 40 40 24 24 d i/o a out bit 0, port 0 p0.1 lcd1 39 39 23 23 d i/o a out bit 1, port 0 www.datasheet.in
cp2400/1/2/3 18 rev. 1.0 p0.2 lcd2 38 38 22 22 d i/o a out bit 2, port 0 p0.3 lcd3 37 37 21 21 d i/o a out bit 3, port 0 p0.4 lcd4 36 36 20 20 d i/o a out bit 4, port 0 p0.5 lcd5 35 35 19 19 d i/o a out bit 5, port 0 p0.6 lcd6 34 34 18 18 d i/o a out bit 6, port 0 p0.7 lcd7 33 33 17 17 d i/o a out bit 7, port 0 p1.0 lcd8 32 32 16 16 d i/o a out bit 0, port 1 p1.1 lcd9 31 31 15 15 d i/o a out bit 1, port 1 p1.2 lcd10 30 30 14 14 d i/o a out bit 2, port 1 p1.3 lcd11 29 29 13 13 d i/o a out bit 3, port 1 p1.4 lcd12 28 28 12 12 d i/o a out bit 4, port 1 p1.5 lcd13 27 27 11 11 d i/o a out bit 5, port 1 p1.6 lcd14 26 26 10 10 d i/o a out bit 6, port 1 p1.7 lcd15 25 25 9 9 d i/o a out bit 7, port 1 p2.0 lcd16 24 24 ? ? d i/o a out bit 0, port 2 p2.1 lcd17 23 23 ? ? d i/o a out bit 1, port 2 table 1. cp2400/1/2/3 pin definitions (continued) name pin numbers type description 48-pin 32-pin spi i 2 c spi i 2 c www.datasheet.in
cp2400/1/2/3 rev. 1.0 19 p2.2 lcd18 22 22 ? ? d i/o a out bit 2, port 2 p2.3 lcd19 21 21 ? ? d i/o a out bit 3, port 2 p2.0 com0 ? ? 8 8 d i/o a out bit 0, port 2 p2.1 com1 ? ? 7 7 d i/o a out bit 1, port 2 p2.2 com2 ? ? 6 6 d i/o a out bit 2, port 2 p2.3 com3 ? ? 5 5 d i/o a out bit 3, port 2 p2.4 lcd20 20 20 ? ? d i/o a out bit 4, port 2 p2.5 lcd21 19 19 ? ? d i/o a out bit 5, port 2 p2.6 lcd22 18 18 ? ? d i/o a out bit 6, port 2 p2.7 lcd23 17 17 ? ? d i/o a out bit 7, port 2 p3.0 lcd24 16 16 ? ? d i/o a out bit 0, port 3 p3.1 lcd25 15 15 ? ? d i/o a out bit 1, port 3 p3.2 lcd26 14 14 ? ? d i/o a out bit 2, port 3 p3.3 lcd27 13 13 ? ? d i/o a out bit 3, port 3 p3.4 lcd28 12 12 ? ? d i/o a out bit 4, port 3 p3.5 lcd29 11 11 ? ? d i/o a out bit 5, port 3 table 1. cp2400/1/2/3 pin definitions (continued) name pin numbers type description 48-pin 32-pin spi i 2 c spi i 2 c www.datasheet.in
cp2400/1/2/3 20 rev. 1.0 p3.6 lcd30 10 10 ? ? d i/o a out bit 6, port 3 p3.7 lcd31 9 9 ? ? d i/o a out bit 7, port 3 p4.0 com0 8 8 ? ? d i/o a out bit 0, port 4 p4.1 com1 7 7 ? ? d i/o a out bit 1, port 4 p4.2 com2 6 6 ? ? d i/o a out bit 2, port 4 p4.3 com3 5 5 ? ? d i/o a out bit 3, port 4 table 1. cp2400/1/2/3 pin definitions (continued) name pin numbers type description 48-pin 32-pin spi i 2 c spi i 2 c www.datasheet.in
cp2400/1/2/3 rev. 1.0 21 figure 4.1. cp2400-gq pinout (spi interface) figure 4.2. cp2401-gq pinout (smbus/i 2 c interface) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 p3.4/lcd28 p0.4/lcd4 p0.2/lcd2 p0.1/lcd1 p0.0/lcd0 nss p0.6/lcd6 p0.5/lcd5 p1.7/lcd15 p1.6/lcd14 p1.4/lcd12 p1.3/lcd11 p0.3/lcd3 cap p1.5/lcd13 clk gnd p3.7/lcd31 p3.5/lcd29 vdd p1.2/lcd10 miso sck xtal1 int rst xtal2 mosi 13 14 15 16 17 18 19 20 21 22 23 24 p1.0/lcd8 p0.7/lcd7 cp2400 - gq top view p4.1/com1 p4.0/com0 p4.3/com3 p4.2/com2 p3.6/lcd30 p1.1/lcd9 p2.0/lcd16 p2.3/lcd19 p2.2/lcd18 p2.1/lcd17 p2.4/lcd20 p2.7/lcd23 p2.6/lcd22 p2.5/lcd21 p3.0/lcd24 p3.3/lcd27 p3.2/lcd26 p3.1/lcd25 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 p3.4/lcd28 p0.4/lcd4 p0.2/lcd2 p0.1/lcd1 p0.0/lcd0 pwr p0.6/lcd6 p0.5/lcd5 p1.7/lcd15 p1.6/lcd14 p1.4/lcd12 p1.3/lcd11 p0.3/lcd3 cap p1.5/lcd13 clk gnd p3.7/lcd31 p3.5/lcd29 vdd p1.2/lcd10 sda smbad0 xtal1 int rst xtal2 scl 13 14 15 16 17 18 19 20 21 22 23 24 p1.0/lcd8 p0.7/lcd7 cp2401 - gq top view p4.1/com1 p4.0/com0 p4.3/com3 p4.2/com2 p3.6/lcd30 p1.1/lcd9 p2.0/lcd16 p2.3/lcd19 p2.2/lcd18 p2.1/lcd17 p2.4/lcd20 p2.7/lcd23 p2.6/lcd22 p2.5/lcd21 p3.0/lcd24 p3.3/lcd27 p3.2/lcd26 p3.1/lcd25 www.datasheet.in
cp2400/1/2/3 22 rev. 1.0 figure 4.3. cp2400-gm pinout (spi interface) figure 4.4. cp2401-gm pinout (smbus/i 2 c interface) p1.2/lcd10 p1.1/lcd9 p1.0/lcd8 p0.7/lcd7 p0.6/lcd6 p0.5/lcd5 33 34 35 31 30 32 p0.4/lcd4 36 p1.3/lcd11 29 p1.6/lcd14 p1.5/lcd13 p1.4/lcd12 27 26 28 p1.7/lcd15 25 gnd xtal2 vdd p4.3/com3 p4.2/com2 p4.1/com1 5 6 7 4 3 2 p4.0/com0 8 xtal1 1 p3.7/lcd31 p3.6/lcd30 p3.5/lcd29 9 10 11 p3.4/lcd28 12 gnd miso mosi nss int rst cap 45 46 47 43 42 44 clk 48 sck 41 p0.2/lcd2 p0.1/lcd1 p0.0/lcd0 39 38 40 p0.3/lcd3 37 p3.2/lcd26 p3.1/lcd25 p3.0/lcd24 p2.7/lcd23 p2.6/lcd22 p2.5/lcd21 17 18 19 15 14 16 p2.4/lcd20 20 p3.3/lcd27 13 p2.3/lcd19 p2.2/lcd18 p2.1/lcd17 21 22 23 p2.0/lcd16 24 cp2400 - gm top view p1.2/lcd10 p1.1/lcd9 p1.0/lcd8 p0.7/lcd7 p0.6/lcd6 p0.5/lcd5 33 34 35 31 30 32 p0.4/lcd4 36 p1.3/lcd11 29 p1.6/lcd14 p1.5/lcd13 p1.4/lcd12 27 26 28 p1.7/lcd15 25 gnd xtal2 vdd p4.3/com3 p4.2/com2 p4.1/com1 5 6 7 4 3 2 p4.0/com0 8 xtal1 1 p3.7/lcd31 p3.6/lcd30 p3.5/lcd29 9 10 11 p3.4/lcd28 12 gnd smba0 sda scl int rst pwr 45 46 47 43 42 44 clk 48 cap 41 p0.2/lcd2 p0.1/lcd1 p0.0/lcd0 39 38 40 p0.3/lcd3 37 p3.2/lcd26 p3.1/lcd25 p3.0/lcd24 p2.7/lcd23 p2.6/lcd22 p2.5/lcd21 17 18 19 15 14 16 p2.4/lcd20 20 p3.3/lcd27 13 p2.3/lcd19 p2.2/lcd18 p2.1/lcd17 21 22 23 p2.0/lcd16 24 cp2401 - gm top view www.datasheet.in
cp2400/1/2/3 rev. 1.0 23 figure 4.5. CP2402-gm pinout (spi interface) figure 4.6. cp2403-gm pinout (smbus interface) 21 22 23 19 18 20 24 17 gnd 5 6 7 4 3 2 8 1 29 30 31 27 26 28 32 25 CP2402 - gm top view 13 14 15 11 10 12 16 9 p0.6/lcd6 p0.5/lcd5 p0.4/lcd4 p0.3/lcd3 p0.2/lcd2 p0.1/lcd1 p0.0/lcd0 p0.7/lcd7 miso mosi nss int rst cap sck clk xtal2 vdd p2.3/com3 p2.2/com2 p2.1/com1 p2.0/com0 xtal1 gnd p1.6/lcd14 p1.5/lcd13 p1.4/lcd12 p1.3/lcd11 p1.2/lcd10 p1.1/lcd9 p1.0/lcd8 p1.7/lcd15 p0.6/lcd6 p0.5/lcd5 p0.4/lcd4 p0.3/lcd3 p0.2/lcd2 p0.1/lcd1 21 22 23 19 18 20 p0.0/lcd0 24 p0.7/lcd7 17 gnd xtal2 vdd p2.3/com3 p2.2/com2 p2.1/com1 5 6 7 4 3 2 p2.0/com0 8 xtal1 1 gnd smba0 sda scl int rst pwr 29 30 31 27 26 28 clk 32 cap 25 cp2403 - gm top view p1.6/lcd14 p1.5/lcd13 p1.4/lcd12 p1.3/lcd11 p1.2/lcd10 p1.1/lcd9 13 14 15 11 10 12 p1.0/lcd8 16 p1.7/lcd15 9 www.datasheet.in
cp2400/1/2/3 24 rev. 1.0 figure 4.7. qfn-48 package drawing notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220, variation vkkd-4 except for features d2 and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.in
cp2400/1/2/3 rev. 1.0 25 figure 4.8. qfn-48 landing diagram ? www.datasheet.in
cp2400/1/2/3 26 rev. 1.0 table 4.1. pcb land pattern dimension min max c1 6.80 6.90 c2 6.80 6.90 e 0.50 bsc x1 0.20 0.30 x2 4.00 4.10 y1 0.75 0.85 y2 4.00 4.10 notes: general 3. all dimensions shown are in millimeters (mm) unless otherwise noted. 4. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 5. this land pattern design is based on ipc-sm-782 guidelines. 6. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 3 x 3 array of 1.20 mm square openings on 1.40 mm pitch should be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.in
cp2400/1/2/3 rev. 1.0 27 figure 4.9. tqfp-48 package diagram table 4.2. tqfp-48 package dimensions dimension min nom max a??1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c0.09?0.20 d9.00 bsc d1 7.00 bsc e0.50 bsc e9.00 bsc e1 7.00 bsc l 0.45 0.60 0.75 aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 ? 0 3.5 7 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-026, variation abc. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components. ? www.datasheet.in
cp2400/1/2/3 28 rev. 1.0 figure 4.10. tqfp-48 recommended pcb land pattern table 4.3. tqfp-48 pcb land pattern dimensions dimension min max c1 8.30 8.40 c2 8.30 8.40 e 0.50 bsc x1 0.20 0.30 y1 1.40 1.50 notes: general: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design: 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly: 7. a no-clean, type-3 solder paste is recommended. 8. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.in
cp2400/1/2/3 rev. 1.0 29 figure 4.11. qfn-32 package drawing table 4.4. qfn-32 package dimensions dimension min typ max dimension min typ max a 0.80 0.9 1.00 e2 3.20 3.30 3.40 a1 0.00 0.02 0.05 l 0.30 0.40 0.50 b 0.18 0.25 0.30 l1 0.00 ? 0.15 d 5.00 bsc aaa ? ? 0.15 d2 3.20 3.30 3.40 bbb ? ? 0.10 e 0.50 bsc ddd ? ? 0.05 e 5.00 bsc eee ? ? 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.in
cp2400/1/2/3 30 rev. 1.0 figure 4.12. typical qfn-32 landing diagram www.datasheet.in
cp2400/1/2/3 rev. 1.0 31 table 4.5. pcb land pattern dimension min max c1 4.80 4.90 c2 4.80 4.90 e 0.50 bsc x1 0.20 0.30 x2 3.20 3.40 y1 0.75 0.85 y2 3.20 3.40 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 3 x 3 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. www.datasheet.in
cp2400/1/2/3 32 rev. 1.0 5. clocking options cp2400/1/2/3 devices include a 20 mhz inte rnal oscillator that is selected as the system clock source upon reset. additional clocking options include an external cmos clock in put, the internal oscillator di vided by 2, 4, or 8, and the smartclock real time clock oscillator. the system cl ock source is selected using the clksel register. the system clock selection may always be overridden by an exter nal cmos clock if the clkovr bit (mscn.2) is set. figure 5.1. clocking options internal register address = 0x32 sfr definition 5.1. cl ksl: clock select bit76543210 name clksl type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:3 unused read = 00000. write = don?t care. 2:0 clksl system clock select . selects the oscillator to be used as system clock source. 000: internal oscillator divided by 1. 001: internal oscillator divided by 2. 010: internal oscillator divided by 4. 011: internal oscillator divided by 8. 100: cmos clock (clk pin). 101: smartclock oscillator. all other values reserved. smartclock oscillator xtal1 xtal2 20 mhz internal oscillator sysclk clksel clksl5 clksl4 clksl3 clksl2 clksl1 clksl0 2 4 8 clk cmos clock 32.768 khz cmos clock mscn clkovr www.datasheet.in
cp2400/1/2/3 rev. 1.0 33 internal register address = 0x33 internal register address = 0x34 sfr definition 5.2. iosccn: in ternal oscillator control bit76543210 name reserved intctl oscen extctl type r/w r/w r/w r/w r/w r/w reset 00000110 bit name function 7:4 unused read = 00000. write = don?t care. 3 reserved read = 0. write = must write 0b. 2 intctl oscillator internal control enable. when set to 1, forces the osc illator to remain enabled. setting this bit to 0 will gate the clock output, but will not disable the oscillator. 1 oscen internal oscillator enable. when set to 0, disables power to the internal oscillator. when set to 1, allows the internal oscillator to be powered (under t he control of intctl and extctl). 0extctl oscillator external control enable. when set to 1 and intctl is cleared to 0, a rising edge on clk will cause the internal oscillator to be disabled. the in ternal oscillator is re-enabled by the next falling edge on clk . note: to control the internal oscillator enable from an external pi n (extctl = 1, intctl = 0), first write both bits to logic 1, then clear the intctl bit. see section ?9.2. ram preservation mode? on page 50 for information on how to place the device in ram preservation mode. when running fr om an external clock, the internal oscillator may be dis- abled by writing 0x00 to iosccn. sfr definition 5.3. revid: revision identification bit76543210 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. indicates the device revision. for example 0x01 indicates revision c. www.datasheet.in
cp2400/1/2/3 34 rev. 1.0 6. internal registers and memory the cp2400/1/2/3 is controlled by internal registers an d provides the system with up to 256 bytes of additional ram. the internal registers and memory are controlled th rough an indirect interface accessible through a 4-wire spi interface (cp2400/2) or 2-wire smbus/i 2 c interface (cp2401/3). a memory map of the internal registers and ram is shown in figure 6.1. the internal registers are listed in ?6.3. internal registers? on page 37. figure 6.1. internal register and ram memory map static ram (256 bytes) 0x0400 ? 0x04ff internal registers 0x0000 ? 0x00ff addrh:addrl reserved 0x0100 ? 0x03ff www.datasheet.in
cp2400/1/2/3 rev. 1.0 35 6.1. accessing internal register s and ram over the spi interface the spi interface supports 6 commands which provide a ccess to all internal registers and ram. the six commands are listed in table 6.1. detailed information on the spi interface including bus timing can be found in section ?14. serial peripheral interface (spi)? on page 101. figure 6.2 shows a typical spi transfer used to access in ternal registers or ram. the first three bytes of the transfer are interpreted as command, addrh, and addrl. on a read, the fourth byte is a wait state in which the spi shift register contents are ignored; st arting with the fifth byte, data transfer begins. on a write, the fourth byte is the first data byte. the direction of data transfer dep ends on the specified command. the spi transaction ends when nss is de-asserted. figure 6.2. spi transfer note: using the ramread command to read an address outside the 0x400?0x4ff range will result in a data value of 0xde. table 6.1. spi command set command opcode description regpoll 0x01 reads data from a single re gister. used for polling a status bit. regread 0x02 reads one or more bytes from registers with sequential addresses. regset 0x03 writes one or more bytes to a single register. used for generating a waveform on a gpio pin or updating the smartclock registers. regwrite 0x04 writes one or more bytes to registers with sequential addresses. ramread 0x06 reads one or more bytes from sequential ram locations. ramwrite 0x08 writes one or more bytes to sequential ram locations. command addrh addrl wait data 0 data n read: command addrh addrl data 0 data 1 data n write: www.datasheet.in
cp2400/1/2/3 36 rev. 1.0 6.2. accessing internal registers and ram over the smbus interface the smbus interface supports 6 commands which provide access to all internal registers and ram. the six commands are listed in table 6.2. detailed information on th e smbus interface including bus timing can be found in section ?15. smbus interface? on page 104. figure 6.3 shows typical smbus read and write transfers used to access internal registers or ram. the first three bytes of a write transfer are interpreted as comman d, addrh, and addrl. for the regpoll, regread, and ramread commands, a repeated start is required to begin data transfer. the host controller may also choose to end the transfer with a stop and then start a new read tr ansfer using the same setup information. for the write and ramwrite command, an smbus write transfer is requ ired. starting with the fourth byte following the slave address, all bytes written are interpreted as data. the smbus transfer ends when the host sends a stop. figure 6.3. smbus transfers note: using the ramread command to read an address outside the 0x400?0x4ff range will result in a data value of 0xde. table 6.2. smbus command set command opcode description regpoll 0x01 reads data from a single re gister. used for polling a status bit. regread 0x02 reads one or more bytes from registers with sequential addresses. regset 0x03 writes one or more bytes to a single register. used for generating a waveform on a gpio pin or updating the smartclock registers. regwrite 0x04 writes one or more bytes to registers with sequential addresses. ramread 0x06 reads one or more bytes from sequential ram locations. ramwrite 0x08 writes one or more bytes to sequential ram locations. p w sla s command a r = read w = write sla = slave address received by cp240x transmitted by cp240x addrh a addrl a a data 0 a data n a smbus write: p w sla s command a addrh a addrl a a a data 0 smbus read (setup): r sla s r a n data n s = start r = repeated start p = stop a = ack n = nack smbus read (data transfer): + data transfer or stop www.datasheet.in
cp2400/1/2/3 rev. 1.0 37 6.3. internal registers the cp2400/1/2/3 internal registers are grouped into categories based on function. the memory map is organized to minimize register access time, by se quentially locating registers that can be read or written with a single block read or write. table 6.3 shows the register memo ry map for all registers available on the device. table 6.3. internal register memory map register address description preserved page no. smartclock registers rtckey 0x0a rtc0 indirect address n 72 rtcadr 0x0b rtc0 indirect data n 73 rtcdat 0x0c rtc0 lock and key n 73 interrupt mask and clocking registers int0en 0x30 interrupt enable register 0 n 43 int1en 0x31 interrupt enable register 1 n 46 clksl 0x32 clock select n 32 iosccn 0x33 internal oscillator control n 33 revid 0x34 revision identifier y 33 interrupt status registers int0rd 0x40 interrupt status register 0 (read-only) n 42 int1rd 0x41 interrupt status register 1 (read-only) n 45 ulpst 0x42 ultra low power status y 55 int0 0x43 interrupt status r egister 0 (self-clearing) n 41 int1 0x44 interrupt status r egister 1 (self-clearing) n 44 timer 0 and timer 1 registers tmr0rll 0x50 timer 0 reload register low byte n 94 tmr0rlh 0x51 timer 0 reload register high byte n 94 tmr0l 0x52 timer 0 low byte n 95 tmr0h 0x53 timer 0 high byte n 95 tmr0cn 0x54 timer 0 control n 93 tmr1rll 0x55 timer 1 reload register low byte n 99 tmr1rlh 0x56 timer 1 reload register high byte n 99 tmr1l 0x57 timer 1 low byte n 100 tmr1h 0x58 timer 1 high byte n 100 tmr1cn 0x59 timer 1 control n 98 smbus registers smbcf 0x68 smbus configuration n 107 ulp/lcd0 data registers lcd0blink 0x80 lcd0 segment blink y 91 ulpmem00 0x81 ulp memory byte 0 y 57 ulpmem01 0x82 ulp memory byte 1 y 57 ulpmem02 0x83 ulp memory byte 2 y 57 www.datasheet.in
cp2400/1/2/3 38 rev. 1.0 ulpmem03 0x84 ulp memory byte 3 y 57 ulpmem04 0x85 ulp memory byte 4 y 57 ulpmem05 0x86 ulp memory byte 5 y 57 ulpmem06 0x87 ulp memory byte 6 y 57 ulpmem07 0x88 ulp memory byte 7 y 57 ulpmem08 0x89 ulp memory byte 8 y 57 ulpmem09 0x8a ulp memory byte 9 y 57 ulpmem10 0x8b ulp memory byte 10 y 57 ulpmem11 0x8c ulp memory byte 11 y 57 ulpmem12 0x8d ulp memory byte 12 y 57 ulpmem13 0x8e ulp memory byte 13 y 57 ulpmem14 0x8f ulp memory byte 14 y 57 ulpmem15 0x90 ulp memory byte 15 y 57 lcd control registers lcd0cn 0x95 lcd0 control y 84 contrast 0x96 lcd0 contrast adjustment y 85 lcd0cf 0x97 lcd0 configuration y 86 lcd0divl 0x98 lcd0 clock divider high byte y 87 lcd0divh 0x99 lcd0 clock divider low byte y 87 lcd0togr 0x9a lcd0 toggle rate y 88 lcd0pwr 0x9b lcd0 power mode y 89 ultra low power control registers mscn 0xa0 master control y 58 mscf 0xa1 master configuration y 59 ulpcn 0xa2 ultra low power control y 54 port i/o configuration registers p0out 0xb0 port 0 output data latch n 66 p1out 0xb1 port 1 output data latch n 66 p2out 0xb2 port 2 output data latch n 66 p3out 0xb3 port 3 output data latch n 66 p4out 0xb4 port 4 output data latch n 66 p0mdi 0xb5 port 0 input mode n 67 p1mdi 0xb6 port 1 input mode n 67 p2mdi 0xb7 port 2 input mode n 67 p3mdi 0xb8 port 3 input mode n 67 p4mdi 0xb9 port 4 input mode n 67 p0mdo 0xba port 0 output mode n 67 p1mdo 0xbb port 1 output mode n 67 p2mdo 0xbc port 2 output mode n 67 p3mdo 0xbd port 3 output mode n 67 table 6.3. internal register memory map (continued) register address description preserved page no. www.datasheet.in
cp2400/1/2/3 rev. 1.0 39 p4mdo 0xbe port 4 output mode n 67 p0drive 0xbf port 0 drive strength n 68 p1drive 0xc0 port 1 drive strength n 68 p2drive 0xc1 port 2 drive strength n 68 p3drive 0xc2 port 3 drive strength n 68 p4drive 0xc3 port 4 drive strength n 68 p0match 0xc4 port 0 match n 64 p1match 0xc5 port 1 match n 64 p2match 0xc6 port 2 match n 64 p3match 0xc7 port 3 match n 64 p4match 0xc8 port 4 match n 64 p0msk 0xc9 port 0 mask n 64 p1msk 0xca port 1 mask n 64 p2msk 0xcb port 2 mask n 64 p3msk 0xcc port 3 mask n 64 p4msk 0xcd port 4 mask n 64 port i/o input and status registers pmatchst 0xd0 port match status n 63 p0in 0xd1 port 0 input n 66 p1in 0xd2 port 1 input n 66 p2in 0xd3 port 2 input n 66 p3in 0xd4 port 3 input n 66 p4in 0xd5 port 4 input n 66 table 6.3. internal register memory map (continued) register address description preserved page no. www.datasheet.in
cp2400/1/2/3 40 rev. 1.0 7. interrupt sources the cp2400/1/2/3 can alert the host processor when any of the interrupt source events listed in table 7.1 triggers an interrupt. the cp2400/1/2/3 alerts the host of pending interrupt events by setting the appropriate flags in the interrupt status registers and driving the int pin low. the int pin will remain asserted unt il all interrupt flags for enabled interrupts have been cleared by the host. interrup t flags are cleared by reading the self-clearing interrupt status registers, int0 and int1. interrupts can be dis abled by clearing the corresponding bits in int0en and int1en. note: when smartclock interrupts are enabled, they are also captured in the ulpst register. if the bits in ulpst are set, then the smartclock interrupt flags in the int0 register will not clear. to clear smartclock interrupt events, first clear the ulpst register then clear int0. if the host processor do es not utilize the int pin, it can periodically read the interrupt status r egisters to determine if any interrupt-generating events have occurred. the int0rd and int1rd read-only registers provide a method of checking for interrupts without clearing the interrupt status registers. table 7.1. interrupt source events event description pending flag enable flag smartclock alarm a smartclock alarm has occurred. int0.4 int0en.4 smartclock oscillato r failure the smartclock oscillator has experienced a failure. int0.3 int0en.3 port match a port match event has occurred. int0.0 int0en.0 reset complete the device is now initialized and ready to communicate over the host interface. int1.4 int1en.4 timer 1 overflow timer 1 has overflowed from 0xffff to 0x0000 or a smartclock capture event has occurred. int1.3 int1en.3 timer 0 overflow timer 0 has overflowed from 0xffff to 0x0000. int1.2 int1en.2 www.datasheet.in
cp2400/1/2/3 rev. 1.0 41 address = 0x43 sfr definition 7.1. int0: interrupt status register 0 (self-clearing) bit76543210 name reserved alrm rtcfail pmint type rrrrrrrr reset 00000000 bit name function 7:6 unused read = 00b. 5 reserved read = 0. 4alrm smartclock alarm interrupt flag. 0: no smartclock alarm pending since alrm was last cleared. 1: smartclock alarm pending. 3rtcfail smartclock oscillator fail interrupt flag. 0: no smartclock oscillator failure events detected sinc e rtcfail was last cleared. 1: smartclock oscillato r failure detected. 2:1 unused read = 00b. 0pmint port match interrupt flag. 0: no port match events detected since pmint was last cleared. 1: port match event pending. www.datasheet.in
cp2400/1/2/3 42 rev. 1.0 address = 0x40 sfr definition 7.2. int0rd: interrup t status register 0 (read-only) bit7 654 3210 name reserved alrmr rtcfailr pmintr type r rrr rrrr reset 0 000 0000 bit name function 7:6 unused read = 00b. 5 reserved read = 0. 4alrmr smartclock alarm interrupt flag. 0: no smartclock alarm pending since alrm was last cleared. 1: smartclock alarm pending. 3rtcfailr smartclock oscillator fail interrupt flag. 0: no smartclock oscillator failure events detected sinc e rtcfail was last cleared. 1: smartclock oscillato r failure detected. 2:1 unused read = 00b. 0pmintr port match interrupt flag. 0: no port match events detected since pmint was last cleared. 1: port match event pending. www.datasheet.in
cp2400/1/2/3 rev. 1.0 43 address = 0x30 sfr definition 7.3. int0en: in terrupt enable register 0 bit76543210 name reserved ealrm ertcfail epmint type r/w r/w r/w r/w r/w r/w r/w r/w reset 11110111 bit name function 7:6 unused read = 11b. write = don?t care. 5 reserved read = varies. write = must write 0b. 4 ealrm enable smartclock alarm interrupt. this bit sets the masking of the smartclock alarm interrupt. 0: disable smartclock alarm interrupts. 1: enable interrupt requests generated by smartclock alarm events. 3ertcfail enable smartclock fail interrupt. this bit sets the masking of the sm artclock oscillato r fail interrupt. 0: disable smartclock oscillator fa il interrupt. 1: enable interrupt reque sts generated by smartc lock oscilla tor failure. 2:1 unused read = 11b. write = don?t care. 0 epmint enable port match interrupt. this bit sets the masking of port match interrupt. 0: disable port match interrupt. 1: enable interrupt requests generated by port match events. www.datasheet.in
cp2400/1/2/3 44 rev. 1.0 address = 0x44 sfr definition 7.4. int1: interrupt status register 1 (self-clearing) bit76543210 name rstc t1f t0f type rrrrrrrr reset 00000100 bit name function 7:5 unused read = 000b. 4rstc reset complete interrupt flag. 0: device has not yet finished initialization. 1: device is ready for communication over the host interface. 3t1f timer 1 overflow interrupt flag. 0: timer 1 has not overflowed and no capture events have occurred since t1f was last cleared. 1: timer 1 has overflowed or a capture event has occurred since t1f was last cleared. 2t0f timer 0 overflow interrupt flag. 0: timer 0has not overflowed since t0f was last cleared. 1: timer 0 has overflowed since t0f was last cleared. 1:0 unused read = 00b. www.datasheet.in
cp2400/1/2/3 rev. 1.0 45 address = 0x41 sfr definition 7.5. int1rd: interrup t status register 1 (read-only) bit76543210 name rstcr t1fr t0fr type rrrrrrrr reset 00010100 bit name function 7:5 unused read = 000b. 4rstcr reset complete interrupt flag. 0: device has not yet finished initialization. 1: device is ready for communication over the host interface. 3t1fr timer 1 overflow interrupt flag. 0: timer 1 has not overflowed and no capture events have occurred since t1f was last cleared. 1: timer 1 has overflowed or a capture event has occurred since t1f was last cleared. 2t0fr timer 0 overflow interrupt flag. 0: timer 0has not overflowed since t0f was last cleared. 1: timer 0 has overflowed since t0f was last cleared. 1:0 unused read = 00b. www.datasheet.in
cp2400/1/2/3 46 rev. 1.0 address = 0x31 sfr definition 7.6. int1en: in terrupt enable register 1 bit76543210 name erstc et1f et0f type r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 bit name function 7:5 unused read = 111. write = don?t care. 4erstc enable reset complete interrupt. 0: disable reset co mplete interrupt. 1: enable interrupt requests generated when de vice is ready for communi cation over the host interface. 3et1f enable timer 1 overflow interrupt. 0: disable timer 1 overflow interrupt. 1: enable interrupt requests generated by timer 1. 2et0f enable timer 0 overflow interrupt. 0: disable timer 0 overflow interrupt. 1: enable interrupt requests generated by timer 0. 1:0 unused read = 11. write = don?t care. www.datasheet.in
cp2400/1/2/3 rev. 1.0 47 8. reset sources reset circuitry allows the cp2400/1/2/3 to be easily placed in a predefined default condition. upon entry to this reset state, the following events occur: ? all direct and indirect registers are in itialized to their defined reset values. ? port i/o pins are forced into a high impedance state with a weak pull-up to v dd . ? the int pin is forced to a logic high state. ? the internal osc illator is stopped. ? all interrupts (except smartclock oscillator fail) are enabled. the cp2400/1/2/3 has two reset sources that place the device in the reset state. the method of entry to the reset state determines the amount of time spent in reset. each of the following reset sources is described in the following sections: ? power-on ? external rst pin upon exit from the reset state, the device automatically st arts the internal oscillator then asserts the interrupt pin. the device is fully functional af ter the interrupt pin is asserted. 8.1. reset initialization after every cp2400/1/2/3 reset, the following initialization procedure is recommended to ensure proper device operation: 1. wait for the reset co mplete interrupt (interrupt pin assertion). 2. disable interrupts (using int0en and int1en on page 43 and page 46) for events that will not be monitored or handled by t he host processor. by defau lt, all interrupts except for smartclock oscilla- tor fail are enabled after every reset. 3. configure the device for the intended mode of operation. www.datasheet.in
cp2400/1/2/3 48 rev. 1.0 8.2. power-on reset during power-up, the cp2 400/1/2/3 is held in the reset state until v dd settles above v rst . a delay (t pordelay ) occurs between the time v dd reaches v rst and the time the device is released from reset. refer to table 3.3 for the electrical characteristics of the power-on reset circuit. figure 8.1. reset timing 8.3. external pin reset the rst pin provides a means for external circuitry to forc e the cp2400/1/2/3 into a reset state. asserting rst for at least t rst will cause the cp2400/1/2/3 to enter the reset state. it is recommended to drive rst with a push-pull driver or add an external pull-up re sistor to avoid erroneous noise-induced resets. the cp2400 /1/2/3 will exit the reset state and generate a reset complete interrupt approximately one t startup delay after a logic high is detected on rst . refer to table 3.3 on page 16 fo r the electrical characteristics. power-on reset /rst t volts 1.0 logic high logic low t pordelay v d d v rst vdd www.datasheet.in
cp2400/1/2/3 rev. 1.0 49 9. power modes the cp2400/1/2/3 has four po wer modes that can be used to minimize overall system power consumption. the power modes vary in device functionality and wake-up met hods. each of the following power modes is explained in the following sections: ? normal mode (device fully functional) ? ram preservation mode (int ernal oscillator disabled) ? ultra low power lcd mode (regulator disabled) ? ultra low power smartclock mode (regulator disabled, lcd disabled) ? shut down mode (all functionality disabled) the power modes above are achieved by disabling specif ic primary functions of the cp2400/1/2/3. figure 9.1 shows how power is distributed throughout the cp2400/1/2 /3. additional secondary functions may also be disabled to save power. these are described in section ?9.8. disabling secondary device functions? on page 58. figure 9.1. power and clock distribution control vdd digital logic ulp lcd control ulp port match smartclock internal oscillator active port match ldo sram timers host interface ulp control logic www.datasheet.in
cp2400/1/2/3 50 rev. 1.0 9.1. normal mode normal mode should be used whenever the host controller is communicating with the cp24 00/1/2/3. in this mode, the device is fully functional and the host interface is capable of operating at full speed. typical normal mode power consumption is listed in table 3.1 on page 12. 9.2. ram preservation mode in ram preservation mode, the internal oscillato r is disabled and the smartclo ck oscillator provides the system clock. ram preservation mode should be used when the cp2400/1/2/3 needs to be active for a prolonged period of time in which communication with the host microcontroller is not required. examples of this include preserving the contents of ram or using the fully featured active port match capabilit ies. lcd and smart clock functionality remains fully functional in ram preservation mode. interrupt latency does increase in this mode. from normal mode, the device can be placed in ram preservation mode using the following procedure: 1. drive the clk pin low. 2. write 0x07 to the iosccn register to synchronize the osc illator control logic. 3. write 0x03 to the iosccn register to switch oscillator control to the clk pin. 4. write 0x05 to the clksl register to sele ct smartclock oscillato r as the system clock. 5. drive the clk pin high. from ram preservation mode, the device can be returned to normal mode using the following procedure: 1. drive the clk pin low. this will force the system cl ock to internal oscillator divided by 1. 2. write 0x06 to the iosccn register to force the internal oscillator to remain enabled. see table 3.4 for ram preservation mode wake-up time. when using the spi interface, the clk pin may be tied to nss in order to wake the device from ram preservation mode on nss falling. the clkovr bit (mscn.2) must be set to logic 0 and the smartclock must be enabled and r unning in order to place the device in ram preservation mode. www.datasheet.in
cp2400/1/2/3 rev. 1.0 51 9.3. ultra low power lcd mode in ultra low power lcd mode, the on-chip ldo is placed in a low power state and power is gated off from all digital logic residing outside the ulp block. the ulp bloc k allows the device to refr esh an lcd, maintain a real time clock, detect smartclock alarm, smartclock oscillator fail, and ulp port match events. the port match functionality in ulp mode differs from the functionalit y of port match when the device is in normal or ram preservation mode. see section ?9.7. port match function ality in the ultra low power modes? on page 56 for more details. all port i/o with the exception of p3.3-p4.3 must be co nfigured to analog mode prior to entering ulp mode. from normal mode, the device can be placed in ulp lcd mode using the following procedure: 1. set int0en:int1en to 0x1900. this enables th e smartclock fail, smartclock alarm, and port match interrupts and disables all others. 2. configure the bandgap into one of its low power modes by writing 0xc0 or 0x80 to mscf. choosing the loose bandgap regu lation (mscf = 0x80) will result in the lowest supply curren t at the expense of increased ripple in the lcd output voltage. 3. drive the pwr or nss pin low. 4. set the lcden (ulpcn.3) to logic 1. if port match functionality is desired, also set the ulpen (ulpcn.1) bit to logic 1. 5. drive the pwr or nss pin high. the device will not enter ulp mode if ther e are pending wake-up events, and the int pin will remain asserted. to ensure that the device has successfully entered the low power mode, the host processor should verify that there are no pending wake-up events prior to placing the device in a ulp mode and that the int pin remains de-asserted for 100 s after placing the device in ulp mode. if the int pin is found to be asserted, then the host controller should treat the situation as if the device has entered ulp and has been awoken by a wake-up event. the state of ram and unpreserved registers should not be relied upon si nce the host controller will not be able to determine if the regulator has been disabled and re-enabled, or ne ver disabled. the port match, smartclock alarm, and smartclock oscillator fa il interrupts should always be enabled any time the device is placed in a ulp mode. once the device enters ulp lcd mo de, it will remain in th is low power mode until a smartclock alarm, smartclock oscillator fail, or ulp port match wake-up event occurs. once the device wakes up, it will generate a reset complete interr upt and assert the int pin. the host controller may also wake up the device at any time. to resume normal mode operation, the host controller should use the following procedure: 1. drive the pwr or nss pin low. 2. wait for the int pin to be asserted. see table 3.4 for ulp mode wake up time. 3. re-initialize all registers which are not preserved du ring ulp mode. see table 6.3 for a list of registers that preserve their state in ulp mode. note: the port i/o state and configuration settings are preserved as long as the device is in the low power mode. upon wake- up, all port i/o state and conf iguration settings will reset, making all port i/o digital inputs with weak pullups enabled. they will remain in this state until t he host controller re-initializes the port i/o state and config uration registers. in the ulp lcd mode, the smartclock oscillator may be disabled if a low frequency cmos clock (~32 khz) is present at clk pin. set the rtcbyp bit (mscn.7) to logic 1 in order to overri de the smartclock with the cmos clock available at the clk pin. the smartclock should be disabled by writing 0x00 to the indirect rtc0cn register instead of setting the rt cdis bit (ulpcn.4) while entering ul p lcd mode. when the smartclock is disabled, smartclock alarm and smartclock oscillator fail detection functionality is no longer available. www.datasheet.in
cp2400/1/2/3 52 rev. 1.0 9.4. ultra low powe r smartclock mode in ultra low power smartclock mode, the on-chip ldo is placed in a low power state and power is gated off from all digital logic residing outside the ulp block. lcd func tionality is disabled. the ulp block allows the device to maintain a real time clock and detect smartclock al arm, smartclock oscillator fail, and ulp port match events. the port match functionality in ulp mode differs from the functionality of port match when the device is in normal or ram preservation mode. see section ?9.7. port match functionality in the ultra low power modes? on page 56 for more details. from normal mode, the device can be placed in ulp smartclock mode using the following procedure: 1. set int0en:int1en to 0x1900. this enables th e smartclock fail, smartclock alarm, and port match interrupts and disables all others. 2. place the bandgap into its lowest power mode by writing 0x80 to mscf. 3. drive the pwr or nss pin low. 4. set the ulpen (ulpcn.1) bit to logic 1. if port matc h functionality is not desired, ensure that all the ulp port mask bits are set to logic 0 by writing 1 to ulprst (ulpcn.1). 5. drive the pwr or nss pin high. the device will not enter any ul p mode if there are pending wake-up events, and the int pin will remain asserted. to ensure that the device has successfully entered the lo w power mode, the host processor should verify that there are no pending wake-up events prior to placing the device in a ulp mode and that the int pin remains de-asserted for 100 us after placing the dev ice in ulp mode. if the int pin is found to be asserted, then the host controller should treat the situation as if the device has entered ulp and has been awoken by a wake-up event. the state of ram and unpreserved registers should not be relied upon si nce the host controller will not be able to determine if the regulator has been disabled and re-enabled, or ne ver disabled. the port match, smartclock alarm, and smartclock oscillator fa il interrupts should always be enabled any time the device is placed in a ulp mode. once the device enters ulp smartclock mode, it will re main in this low power mode until a smartclock alarm, smartclock oscillator fail, or ulp port match wake-up event occurs. once the device wakes up, it will generate a reset complete interr upt and assert the int pin. the host controller may also wake up the device at any time. to resume normal mode operation, the host controller should use the following procedure: 1. drive the pwr or nss pin low. 2. wait for the int pin to be asserted. see table 3.4 for ulp mode wake up time. 3. re-initialize all registers which are not preserved du ring ulp mode. see table 6.3 for a list of registers that preserve their state in ulp mode. note: the port i/o state and configuration settings are preserved as long as the device is in the low power mode. upon wake- up, all port i/o state and conf iguration settings will reset, making all port i/o digital inputs with weak pullups enabled. they will remain in this state until t he host controller re-initializes the port i/o state and config uration registers. in the ulp smartclock m ode, the smartclock oscillator may be disa bled if a low frequency cmos clock (~32 khz) is present at clk pin. set the rtcbyp bit (mscn.7) to logic 1 in order to override the smartclock with the cmos clock available at the clk pin. the smartclock should be disabled by writing 0x00 to the indirect rtc0cn register instead of setting the rtcdis bit (ulp cn.4). when the smartclock is disabled, smartclock alarm and smartclock oscilla tor fail detection functiona lity is no longer available. www.datasheet.in
cp2400/1/2/3 rev. 1.0 53 9.5. shutdown mode shutdown mode is the lowest power mode for the cp2400/1 /2/3. all device functionality is disabled in this mode and a reset is required to wake up the device. this mode is typically used when the device is not needed for prolonged periods of time. from normal mode, the device can be placed in shutdown mode using the following procedure: 1. set int0en:int1en to 0x1900. this enables th e smartclock fail, smartclock alarm, and port match interrupts and disables all others. 2. ensure that all ulp port mask bits are set to logic 0 by writing 1 to ulprst (ulpcn.1). 3. configure the bandgap for shutdown mode by writing 0x80 to mscf. 4. drive the pwr or nss pin low. 5. set the rtcdis (ulpcn.4) and the ulpen (ulpcn.1) bit to logic 1. 6. drive the pwr or nss pin high. the device will not enter shutdown if ther e are pending wake-up events, and the int pin will remain asserted. to ensure that the device has successfully entered the low power mode, the host processor should verify that there are no pending wake-up events prior to placing the device in shutdown mode and that the int pin remains de- asserted for 100 s after placing the device in shutdown mode. if the int pin is found to be asserted after the device has been placed in shutdown, the device should be reset and placed in shutdown again. it is essential that all ulp port mask bits be set to logic 0 before the device is placed in shutdo wn in order to prevent the possibility of a partial wake-up due to a port matc h event. the port match, smartclock alarm, and smart clock oscillator fail interrupts should always be enabled any time the device is placed in shutdown mode. note: the port i/o state and configuration settings are preserved as long as the device is in shutdown. upon reset, all port i/o state and configuration settings will reset, making all port i/o digital inputs with weak pull-ups enabled. they will remain in this state until the host controller re-initializ es the port i/o state and configuration registers. www.datasheet.in
cp2400/1/2/3 54 rev. 1.0 address = 0xa2 note: the state of ulppmpol should not be changed in the same write which enables the ulp modes. rather, the state of ulppmpol should be set first, then the ulp mode should be enabled. sfr definition 9.1. ulpcn: ultr a low power control register bit7654321 0 name rtcdis lcden reserved ulpen ulppmpol type r/w r/w r/w r/w r/w r/w r/w r/w reset 0000000 0 bit name function 7:5 unused read = 000b. write = don?t care. 4rtcdis ultra low power mode smartclock disable. when set to 1, the sm artclock oscillator will be disabled tw o smartclock cycles after entry into ulp mode. this allows the device to enter its shutdown mode. any write operation that sets this bit to 1b must also set ulpen to 1b. 3lcden ultra low power lcd enable. when set to 1, lcd functionality is enable d in ulp mode. rising edge transitions on nss and pwr disable the internal ldo and place the device into the ultra low power mode. a falling edge transition on nss or pwr will re-enable the regulator and return the device to normal power mode. this bit is self-clearing upon wake-up from the ultra low power mode. 2 reserved read = 0b. must write 0b. 1 ulpen ultra low power port match enable. when set to 1, port match functionality is enabled in ulp mode. rising edge transitions on nss and pwr disable the internal ldo and place the device into the ultra low power mode. a falling edge transition on nss or pwr will re-enable the regulator and return the device to normal power mode. this bit is self-clearing upon wake-up from the ultra low power mode. 0 ulppmpol ultra low power port match polarity. 0: ulp port match wake-up occurs on risi ng edge transitions (level sensitive). 1: ulp port match wake-up occurs on fa lling edge transitions (level sensitive). www.datasheet.in
cp2400/1/2/3 rev. 1.0 55 9.6. determining the ul p mode wake-up source after waking from ulp mode, the ulpst register may be used to determine the cause of wake up. the three pos- sible wake up sources are smartclock alarm, smartclock oscillator failure, a nd ulp port match. if none of the bits in ulpst are set, then the wake up was due to the nss or pwr pin falling edge. this register may be cleared by writing a 1 to the clear (mscn.6) bit in the master control register. address = 0x42 sfr definition 9.2. ulpst: ultr a low power status register bit76543 2 1 0 name rtcfail rtcalrm ulppm type rrrrr r r r reset 00000 0 0varies bit name function 7:3 unused read = 00000b. write = don?t care. 2rtcfail smartclock oscillator fail wake up indicator. 0: source of last wa ke up was not a smartclock oscillator fail. 1: source of last wake up was a smart clock oscillator fail. 1rtcalrm smartclock alarm wake up indicator. 0: source of last wake up was not a smartclock alarm. 1: source of last wake up was a smartclock alarm. 0 ulppm ultra low power port match wake up indicator. 0: source of last wake up was not a ulp port match. 1: source of last wake up was a ulp port match. www.datasheet.in
cp2400/1/2/3 56 rev. 1.0 9.7. port match functionality in the ultra low power modes the ultra low power lcd and smartclock modes support port match wake-up. ulp smartclock mode supports port match on all p0, p1, p2, and p3 pins. ulp lcd mo de supports port match on p3.3, p3.4, p3.5, p3.6, and p3.7. ulp port match events can be gen erated on rising or falling edges; however, all events are configured to the same polarity using the ulppmpol bit (ulpcn.0). ulp port match is level sensitive and a new port match event will be generated every clock cyc le as long as the i/o state matches th e polarity set by the ulppmpol bit. note: in ulp lcd mode, when using a 4-mux lcd, port match may only be used to detect rising edges. each port i/o that particip ates in ulp port match is individually ma skable to allow or disallow the generation of port match events. the most significant bit in each 4-bi t nibble of ulp memory controls the masking of a single port i/o. for example, the masking of p3.4 and p3.5 ar e controlled by bit 3 and bit 7 of ulpmem14, respectively. table 9.1 and table 9.2 show the ulp mask bit locations for all i/o capable of port match when the device is in ulp smartclock and ulp lcd m ode, respectively. a mask setting of 0 will prevent the ge neration of port match events from the specified i/o and a mask setting of 1 will allow gene ration of port match ev ents from the specified i/o. port i/o to be used for ulp port match must be co nfigured as digital pins. setting the ulprst (ulpcn.1) to logic 1 will reset all port mask bits to 0. ulp port match is enabled upon entry into ulp mode when the ulpen bit (ulpcn.1) is set to logic 1 and disabled upon wake-up from ulp mode. the ulpst register may be used to determine when a ulp port match event has occurred. when enabled, the port match interrupt will occur when an active mode port match or ulp port match event occurs. table 9.1. ulp smartclock port match mask bit locations ulp memory bit 7 masks bit 3 masks ulpmem00 p0.1 p0.0 ulpmem01 p0.3 p0.2 ulpmem02 p0.5 p0.4 ulpmem03 p0.7 p0.6 ulpmem04 p1.1 p1.0 ulpmem05 p1.3 p1.2 ulpmem06 p1.5 p1.4 ulpmem07 p1.7 p1.6 ulpmem08 p2.1 p2.0 ulpmem09 p2.3 p2.2 ulpmem10 p2.5 p2.4 ulpmem11 p2.7 p2.6 ulpmem12 p3.1 p3.0 ulpmem13 p3.3 p3.2 ulpmem14 p3.5 p3.4 ulpmem15 p3.7 p3.6 table 9.2. ulp lcd port match mask bit locations ulp memory bit 7 masks bit 3 masks ulpmem13 p3.3 n/a ulpmem14 p3.5 p3.4 ulpmem15 p3.7 p3.6 www.datasheet.in
cp2400/1/2/3 rev. 1.0 57 addresses: ulpmem00 = 0x81, ulpmem01 = 0x82, ulpmem02 = 0x83, ulpmem03 = 0x84, ulpmem04 = 0x85, ulpmem05 = 0x86, ulpmem06 = 0x87, ulpmem07 = 0x88, ulpmem08 = 0x89, ulpmem09 = 0x8a, ulpmem10 = 0x8b, ulpmem11 = 0x8c, ulpmem12 = 0x8d, ulpmem13 = 0x8e, ul pmem14 = 0x8f, ulpmem15 = 0x90. sfr definition 9.3. ulpmemn: ulp memory bit76543210 name ulpmemn type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 ulpmemn ulp memory. each nibble controls one i/o pin. see ?12.5. mapping ulp memory to lcd pins? on page 90 for information on how ulp memory is used with the lcd function. see section ?9.7. port match functionality in the ultra low power modes? on page 56 for information on how ulp memory is us ed with the ulp port match function. www.datasheet.in
cp2400/1/2/3 58 rev. 1.0 9.8. disabling sec ondary device functions the mscn and mscf registers provide additional ways of saving power by disabling unnecessary functionality. address = 0xa0 sfr definition 9.4. mscn: master control register bit765432 1 0 name rtcbyp clear adrinv rtcod sramd clkovr ulprst lcden type r/w r/w r/w r/w r/w r/w r/w r/w reset 000000 0 0 bit name function 7 rtcbyp smartclock oscillator bypass. when set to 1, the smartclock osc illator clock is bypa ssed and the clk pin is used to drive the low frequency clock used for ulp operations. 6 clear ulp status clear. writing 1 to this register clears all bits in the ulp status register (ulpst). 5adrinv sram address invert. when set to 1, the least significant byte of th e sram target address is inverted. th is allows the sram to be accessed in reverse sequential order using a single block read or write. for example, a block read from addresses 0x0400 to 0x04ff will return data from ram locations 0x04ff to 0x0400. 4rtcod smartclock oscillator output disable. when set to 1, the smartclock oscillator output is gated off, and does not drive the low frequency clock used for ulp operations. 3sramd sram disable. 0: the sram is enabled. 1: the sram is disabled. 2clkovr system clock override. 0: the clksl register determines the system clock. 1: the system clock is the cmos clock input through the clk pin. 1ulprst ulp memory reset. writing 1 to this bit clears all values in the ulp memory to 0x00. this bit can be used to quickly set all ulp port mask bits to logic 0. 0lcden lcd enable. 0: lcd functionality is disabled. 1: lcd functionality is enabled. www.datasheet.in
cp2400/1/2/3 rev. 1.0 59 address = 0xa1 note: when the band gap is configured for low power mode with loose voltage regulation, the lcd0cf register should be adjusted so that charge pump cycles occur at least once every 2 ms. sfr definition 9.5. mscf: mast er configuration register bit765432 1 0 name bgmd[1:0] reserved reserved r eserved reserved reserved cpbyp type r/w r/w r/w r/w r/w r/w r/w r/w reset 000000 0 0 bit name function 7:6 bgmd[1:0] band gap power mode. 00: band gap is in normal power mode. 01: reserved. 10: band gap is configured for low power with loose voltage regulation (required setting for shutdown mode). 11: band gap is configured for low power with tight voltage regulation. 5:1 reserved read = varies. must write 00000b. 0 cpbyp charge pump bypass. when set to 1, the charge pump is bypassed and disabled. vdd is used as the vlcd supply voltage. www.datasheet.in
cp2400/1/2/3 60 rev. 1.0 10. port input/output cp2400/1/2/3 devices have 36 (48-pin packages) or 20 (32-pin packages) mult i-function i/o pins. port pins are organized as byte-wide ports and may be used for general purpose i/o, generating a port match interrupt, or for an analog function (e.g., lcd). note: the port match functionality described in this chapter only applies when the device is awake (normal and idle power modes). refer to the power modes chapter for information on port match wake-up from ulp or shutdown mode. all port i/os are 5 v tolerant when used as digital inputs or open-drain outputs. for port i/os configured as digital push-pull outputs, curren t is sourced from the v dd supply. see section 10.1 for more information on port i/o operating modes and the electrical spec ifications chapter for detailed electr ical specifications . figure shows a block diagram of the port i/o for the 48-pin packaged de vices. the 32-pin packaged devices are functionally the same, however, they have le ss i/o. refer to the system overview for a detailed block diagram of 32-pin devices. figure 10.1. port i/o diagram configuration registers port mapping logic p0 i/o cells p0.0 p0.7 (internal analog signals) 36 lcd p1 i/o cells p1.0 (port latches -- digital) p2 (p0.0-p0.7) (p3.0-p3.7) 8 8 p3 p4 (p4.0-p4.3) 4 8 pnmdo, pnmdi registers p1.7 p2 i/o cells p3 i/o cells p4 i/o cells p2.0 p2.7 p3.0 p3.7 p4.0 p4.3 4 8 8 8 p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 port match www.datasheet.in
cp2400/1/2/3 rev. 1.0 61 10.1. port i/o modes of operation all port pins use the port i/o cell shown in figure 10.2. ea ch port i/o cell can be configured by software for analog i/o or digital i/o using the pnmdi registers. on reset or wake-up from ulp mode, all port i/o cells default to a digital high impedance state with weak pull-ups enabled. 10.1.1. port pins configured for analog i/o any pins to be used for lcd should be configured for analog i/o (pnmdi.n = 0). when a pin is configured for analog i/o, its weak pullup and digital output driver and receiver are disabled. port pins configured for analog i/o will always read back a value of 0 regardless of the actual voltage on the pin. 10.1.2. port pins configured for digital i/o any pins to be used for gpio or port match should be co nfigured as digital i/o (pnmdi.n = 1). for digital i/o pins, one of two output modes (push-pull or open-drain) must be selected usin g the pnmdo registers. push-pull outputs (pnmdo.n = 1) always drive the port pad to the v dd or gnd supply rails based on the output logic value of the port pin. open-drain outputs have the high side driver disabl ed; therefore, they only drive the port pad to gnd when the output logic value is 0 and become high impedance inputs (both high and low drivers turned off) when the output logic value is 1. when a digital i/o cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the vdd supply voltage to ensure the digital input is at a defined logic state. weak pullups are disabled when the i/o cell is driven to gnd to minimize power cons umption. the user must ensure that digital i/o are always internally or externally pulled or driven to a valid logic state. an analog signal applie d to a digital i/o pin will result in increased power consumption. figure 10.2. port i/o cell block diagram gnd vdd vdd (weak) port pad to/from analog peripheral pxmdi.x (1 for digital) (0 for analog) pxout.x ? output logic value (port latch) pxin.x ? input logic value (reads 0 when pin is configured as an analog i/o) pxmdo.x (1 for push-pull) (0 for open-drain) www.datasheet.in
cp2400/1/2/3 62 rev. 1.0 10.1.3. interfacing port i/o to 5 v and 3.3 v logic all port i/os configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than 4.5 v and less than 5.25 v. wh en the supply voltage is in the range of 1.8 to 2.2 v, the i/o may also interface to digital logic operating between 3.0 to 3.6 v. an external pull-up resistor to the higher supply voltage is typically required for most systems. important notes: ? when interfacing to a signal that is between 4.5 and 5.25 v, the maximum clock frequency that may be input on a gpio pin is 12.5 mhz. the exception to this rule is when routing an external cmos clock to p0.3, in which case a signal up to 25 mhz is valid as long as the rise time (10% to 90%) is shorter than 1.8 ns. ? when the supply voltage is less than 2.8 v and interf acing to a signal that is between 3.0 and 3.6 v, the maximum clock frequency that may be in put on a gpio pin is 3.125 mhz. the exception to this rule is when routing an external cmos clock to p0.3, in which case a signal up to 25 mhz is valid as long as the rise time (10% to 90%) is shorter than 1.2 ns. ? in a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least 150 a to flow into the port pin when the supply voltage is between (vdd_mcu/dc+ plus 0.4 v) and (vdd_mcu/dc+ plus 1.0 v). once the port pad voltage increases beyond this range, the current flowing into the port pin is minimal. ? these guidelines only apply to multi-voltage interfaces. port i/os may always interface to digital logic operating at the same supply voltage. 10.1.4. increasing port i/o drive strength port i/o digital output drivers support a high and low dr ive strength; the default is low drive strength. the drive strength of a port i/o can be configur ed using the pndrive registers. see table 3.2 on page 13 for the difference in output drive strength between the two modes. 10.2. assigning port i/o pins to analog and digital functions port i/o pins are multi-function and may be used for mu ltiple purposes. the following process can be used to assign gpio pins to their appropriate function. 1. determine the pins to be used for the lcd function. these pins need to be configured for analog i/o. 2. any remaining unused pins may be used for gpio or port match. these pins need to be configured for digital i/ o. note: ulp port match is only available on a lim ited number of pins. see section ?9.7. port match functionality in the ultra low power modes? on page 56 for more details. all port i/o with the exception of p3.3?p4.3 must be configured to analog mode prior to entering ulp mode. www.datasheet.in
cp2400/1/2/3 rev. 1.0 63 10.3. active mode port match port match functionality allows system events to be tr iggered by a logic value change on a gpio pin. a software controlled value stored in the pnmatch registers specifies the expected or normal logic values of the associated port. a port mismatch event occurs if the logic levels of the port?s input pins no longer match the software controlled value. this allows software to be notified if a certain change or pattern occurs on an input pin. the pnmsk registers can be used to individually sele ct which pins should be compared against the pnmatch registers. a port mismatch event is generated if (pnin & pnmsk) does not equal (pnmatch & pnmsk) for all ports. a port mismatch event may be used to generate an interrupt. see ?7. interrupt sources? on page 40 for more details on handling an interrupt. address = 0xd0 sfr definition 10.1. pmatchst: port match status register bit76543210 name p4m p3m p2m p1m p0m type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 unused read = 000b. write = don?t care. 4p4m port 4 match. 0: no port mismatch events have been detected on p4. 1: a port mismatch event is present on p4. 3p3m port 3 match. 0: no port mismatch events have been detected on p3. 1: a port mismatch event is present on p3. 2p2m port 2 match. 0: no port mismatch events have been detected on p2. 1: a port mismatch event is present on p2. 1p1m port 1 match. 0: no port mismatch events have been detected on p1. 1: a port mismatch event is present on p1. 0p0m port 0 match. 0: no port mismatch events have been detected on p0. 1: a port mismatch event is present on p0. www.datasheet.in
cp2400/1/2/3 64 rev. 1.0 address: p0msk = 0xc9; p1msk = 0xca; p2 msk = 0xcb; p3msk = 0xcc; p4msk = 0xcd address: p0match = 0xc4; p1match = 0xc5; p2 match = 0xc6; p3match = 0xc7; p4match = 0xc8 sfr definition 10.2. pnmsk : port n mask register bit76543210 name pnmsk[7:0] type r/w reset 00000000 bit name function 7:0 pnmsk[7:0] port n mask value. selects the pn pins to be compared with the corresponding bits in pnmatch. 0: pn.x pin pad logic value is ignored and cannot cause a port mismatch event. 1: pn.x pin pad logic value is compared to pnmatch.x. sfr definition 10.3. pnmatch : port n match register bit76543210 name pnmatch[7:0] type r/w reset 11111111 bit name function 7 : 0pnmatch[7:0] port n match value. match comparison value used on port n for bits whose pnmsk is set to 1. 0: pn.x pin logic value is compared with logic low. 1: pn.x pin logic value is compared with logic high. www.datasheet.in
cp2400/1/2/3 rev. 1.0 65 10.4. registers for accessing and configuring port i/o all port i/o are accessed and configured through registers. when writing to a port, the value written to the pnout register is latched to maintain the output data value at each pin. when reading, the logi c levels of the port's input pins are returned in the pnin. if the pnout register is read , the value returned will be t he value of the output latch, not the logic level of the port pad. the pnin register is read only. the port input mode of the i/o pins is defined using th e port input mode registers (pnmdi). each port cell can be configured for analog or digital i/o. the output driver charac teristics of the digital i/o pins are defined using the port output mode registers (pnmdo). each port output driver can be configured as either open drain or push-pull. to configure a pin as a digital input, configure it as an open drain output and write 1 to its port latch. the drive strength of the output driver s are controlled by the port drive stre ngth (pndrive) registers. the default is low drive strength. see table 3.2 on page 13 for the diff erence in output drive strength between the two modes. www.datasheet.in
cp2400/1/2/3 66 rev. 1.0 address: p0out = 0xb0; p1 out = 0xb1; p2out = 0xb2; p3out = 0xb3; p4out = 0xb4 address: p0in = 0xd1; p1in = 0xd2; p2 in = 0xd3; p3in = 0xd4; p4in = 0xd5 sfr definition 10.4. pnout: port n output latch bit76543210 name pnout[7:0] type r/w reset 11111111 bit name function 7:0 pnout[7:0] port n output latch. sets or reads the port latch logic value. 0: pn.x output latch is logic low. 1: pn.x output latch is logic high. sfr definition 10.5. pnin: port n input bit76543210 name pnin[7:0] type r reset 11111111 bit name function 7:0 pnin[7:0] port n input. reads the port pin logic state in port cells configured for digital i/o. 0: pn.x port pin is logic low. 1: pn.x port pin is logic high. www.datasheet.in
cp2400/1/2/3 rev. 1.0 67 address: p0mdi = 0xb5; p1mdi = 0xb6; p2 mdi = 0xb7; p3mdi = 0xb8; p4mdi = 0xb9 address: p0mdo = 0xba; p1mdo = 0xbb; p2 mdo = 0xbc; p3mdo = 0xbd; p4mdo = 0xbe sfr definition 10.6. pnmdi: port n input mode bit76543210 name p0mdi[7:0] type r/w reset 11111111 bit name function 7:0 pnmdi[7:0] pn analog configuration bits. port pins configured for analog mode have t heir weak pullup, digital driver, and digital receiver disabled. 0: corresponding pn.x pin is configured for analog i/o. 1: corresponding pn.x pin is configured for digital i/o. sfr definition 10.7. pnmdo : port n output mode bit76543210 name pnmdo[7:0] type r/w reset 00000000 bit name function 7:0 pnmdo[7:0] pn output configuration bits. 0: corresponding pn.x output is open-drain. 1: corresponding pn.x output is push-pull. www.datasheet.in
cp2400/1/2/3 68 rev. 1.0 address: p0drive = 0xbf; p1dr ive = 0xc0; p2drive = 0xc1; p3drive = 0xc2; p4drive = 0xc3 sfr definition 10.8. pndrive : port n drive strength bit76543210 name pndrive[7:0] type r/w reset 00000000 bit name function 7:0 pndrive[7:0] pn drive strength configuration bits. configures digital i/o port cells to high or low output drive strength. 0: corresponding pn.x has low output drive strength. 1: corresponding pn.x has high output drive strength. www.datasheet.in
cp2400/1/2/3 rev. 1.0 69 11. smartclock (real time clock) cp2400/1/2/3 devices include an ultra lo w power 32-bit smartclock peripheral (real time clock) with alarm. the smartclock has a dedicated 32 khz oscillator that can be configured for use with or without a crystal. no external resistor or loading capacitors are required. the on-chip loading capacitors are programmable to 16 discrete levels allowing compatibilit y with a wide range of crystals. the smartclock allows a maximum of 36 hour 32-bit independent time-keeping when used with a 32.768 khz watch crystal. the smartclock provides an alarm an d missing smartclock events, which could be used to wake up from the ultra low power mode. figure 11.1. smartclock block diagram smartclock oscillator smartclock host interface xtal2 xtal1 rtc0cn capturen rtc0xcf rtc0xcn alarmn rtc0key rtc0adr rtc0dat interface registers internal registers smartclock state machine 32-bit smartclock timer programmable load capacitors interrupt www.datasheet.in
cp2400/1/2/3 70 rev. 1.0 11.1. smartclock interface the smartclock interface consists of three registers: rtckey, rtcadr, and rtcdat. these interface registers are located on the cp2400/1/2/3 register map and provid e access to the smartclock internal registers listed in table 11.1. the smartclock internal registers can only be accessed indirectly through the smartclock interface. 11.1.1. smartclock lock and key functions the smartclock interface is protected with a lock and key function. the smartclock lock and key register (rtckey) must be written wit h the correct key codes, in sequence, be fore writes and reads to rtcadr and rtcdat may be performed. the key codes are: 0xa5, 0xf1 . there are no timing restrictions, but the key codes must be written in order. if th e key codes are written out of order, the wrong codes are written, or an indirect register read or write is attempted while t he interface is locked, the smartclo ck interface will be disabled, and the rtcadr and rtcdat registers will become inaccessible until the next system reset. once the smartclock interface is unlocked, software may perform any number of accesses to the smart clock registers until the interface is re-locked or th e device is reset. any writ e to rtckey while the smartclo ck interface is unlocked will re-lock the interface. reading the rtckey register at any ti me will provide the smartclock interf ace status and will not interfere with the sequence that is being written. t he rtckey register description in sfr definition 11.1 lists the definition of each status code. table 11.1. smartclock internal registers smartclock address smartclock register register name description 0x00?0x03 capturen smartclock capture registers four registers used for setting the 32-bit smartclock timer or reading its current value. 0x04 rtc0cn smartclock control register controls the operation of the smartclock state machine. 0x05 rtc0xcn smartclock oscillator control register controls the operation of the smartclock oscillator. 0x06 rtc0xcf smartclock oscillator configuration register controls the value of the progammable oscillator load capaci tance and enables/ disables autostep. 0x08?0x0b alarmn smartclock alarm registers four registers used for setting or reading the 32-bit smartclock alarm value. www.datasheet.in
cp2400/1/2/3 rev. 1.0 71 11.1.2. using rtcadr and rtcdat to access smartclock internal registers the smartclock internal registers can be read and written using rtcadr and rtcdat. the rtcadr register selects the smartclock internal register that will be targeted by s ubsequent reads or writes. a smartclock write operation is initiat ed by writing to the rtcdat register. below is an example of writing to a smartclock internal register. 1. write 0x05 to rtcadr. this se lects the internal rtc0cn register at smartclock address 0x05. 2. write 0x00 to rtcdat. this operation writ es 0x00 to the internal rtc0cn register. a smartclock read operation is in itiated by setting the smartclock in terface busy bit. this transfers the contents of the internal regi ster selected by rtcadr to rtcdat. the tr ansferred data will remain in rtcdat until the next read or write operation. below is an ex ample of reading a smartclock internal register. 1. write 0x05 to rtcadr. this se lects the internal rtc0cn register at smartclock address 0x05. 2. write 1 to busy. this initiates th e transfer of data from rtc0cn to rtcdat. note: step 1 and step 2 may be combined into a single write. 3. read data from rtcdat. this data is a copy of the rtc0cn register. 11.1.3. smartclock interface autoread feature when autoread is enabled, each read from rtcdat initiates the next indirect read operation on the smartclock internal register selected by rtcadr. software should set the busy bit once at the beginning of each series of consecutive reads. software must check if the smartclock interface is busy prior to reading rtcdat. autoread is enabled by setting autord (rtcadr.6) to logic 1. 11.1.4. rtcadr autoincrement feature for ease of reading and writing the 32-bit capture and alarm values, rtcadr automa tically increments after each read or write to a capturen or alarmn register. th is speeds up the process of setting an alarm or reading the current smartclock ti mer value by allowing all 4 capture or alarm registers to be read or written in a single block write. autoincrement is always enabled. notes: autoincrement should only be used with block reads/writes . when using single-byte reads/writes, rtcadr must be written before each data read or write. when using smbus to perform a block read/write, the rtcadr register must be written using the regset command. www.datasheet.in
cp2400/1/2/3 72 rev. 1.0 address = 0x0a sfr definition 11.1. rtckey: smartclock lock and key bit76543210 name rtc0st[7:0] type r/w reset 00000000 bit name function 7:0 rtc0st smartclock interface lock/key and status. locks/unlocks the smartclock interface when written. provides lock status when read. read: 0x00: smartclock interface is locked. 0x01: smartclock interface is locked. first key code (0xa5) has been written, waiting for second key code. 0x02: smartclock interface is unlocked. first and second key codes (0xa5, 0xf1) have been written. 0x03: smartclock interface is disabled until the next system reset. write: when rtc0st = 0x00 (locked), writing 0xa5 followed by 0xf1 unlocks the smart- clock interface. when rtc0st = 0x01 (waiting for second key code), writing any value other than the second key code (0xf1) will change rtc0stat e to 0x03 and disable the smartclock interface until the next system reset. when rtc0st = 0x02 (unlocked), any write to rtckey will lo ck the smartclock interface. when rtc0st = 0x03 (disabled), wr ites to rtckey have no effect. www.datasheet.in
cp2400/1/2/3 rev. 1.0 73 address = 0x0b address = 0x0c sfr definition 11.2. rtca dr: smartclock address bit76543210 name busy autord short addr[3:0] type r/w r/w r r/w r/w reset 0 0 0 0 varies varies varies varies bit name function 7busy smartclock interface busy indicator. indicates smartclock interface status. writin g 1 to this bit initiates an indirect read. 6autord smartclock interface autoread enable. enables/disables autoread. 0: autoread disabled. 1: autoread enabled. 5 unused read = 0b; write = don?t care. 4short short strobe enable. enables/disables the short strobe feature. it is recommended to always enable the short strobe feature to minimi ze the read/write time. 0: short strobe disabled. 1: short strobe enabled. 3:0 addr[3:0] smartclock indirect register address. sets the currently select ed smartclock register. see table 11.1 for a listing of all smartclock indirect registers. note: the addr bits increment after each indirect read/write operation that targets a capturen or alarmn internal smartclock register. autoincrement should only be used with block reads/writes. sfr definition 11.3. rtcdat: smartclock data bit76543210 name rtcdat[7:0] type r/w reset 00000000 bit name function 7:0 rtcdat smartclock data bits. holds data transferred to/from the internal smartclock register selected by rtcadr. www.datasheet.in
cp2400/1/2/3 74 rev. 1.0 11.2. smartclock clocking sources the smartclock peripheral is clocked from its own timebase, independent of the system clock. the smartclock timebase is derived from the smartclock oscillator circ uit, which has two modes of operation: crys tal mode, and self-oscillate mode. the oscillation fr equency is 32.768 khz in crystal mode and can be programmed in the range of sub 20 khz to above 40 khz in self -oscillate mode. in crystal mode, xtal1 and xtal2 ma y be overdriven by an external cmos clock. 11.2.1. using the smartclock oscillator with a crystal or external cmos clock when using crystal mode, a 32.768 khz crystal should be connected between xtal3 and xtal4. no other external components are required. th e following steps show how to start the smartclock crystal oscillator in software: 1. set smartclock to crystal mode (xmode = 1). 2. optional. enable/disable automatic gain control (agcen) and bias doubling (biasx2). see section 11.2.4 for recommendations on using these oscillator features. 3. set the desired loading capacitance (rtc0xcf). 4. enable power to the smartclock oscillato r circuit (rtc0en = 1). 5. wait 2 ms. 6. poll the smartclock clock va lid bit (clkvld) until the crystal oscillator stabilizes. 7. poll the smartclock load capacitance ready bi t (loadrdy) until the load capacitance reaches its programmed value. 8. enable the smartclock missing clock detector. 9. wait 2 ms. 10.clear the pmu0cf wake-up source flags. in crystal mode, the smartclock osc illator may be driven by an external cm os clock. the cmos clock should be applied to both xtal1 and xtal2. the input low voltage (vil) and input high voltage (vih) for these pins when used with an external cmos clock are 0.1 and 0.8 v , respectively. the smartclock oscillator should be configured to its lowest bias setting with agc disabl ed. the clkvld bit is indete rminate when using a cmos clock, however, the oscfail bit may be checked 2 ms afte r smartclock oscillator is powered on to ensure that there is a valid clock. 11.2.2. using the smartclock oscillator in self-oscillate mode the following steps show how to configure smartclock for use in self-oscillate mode: 1. set smartclock to self-osc illate mode (xmode = 0). 2. set the desired oscillation frequency: for oscillation at about 20 khz, set biasx2 = 0. for oscillation at about 40 khz, set biasx2 = 1. 3. the oscillator starts oscillating instantaneously. 4. fine tune the oscillation frequency by adjusting the load capacitance (rtc0xcf). www.datasheet.in
cp2400/1/2/3 rev. 1.0 75 11.2.3. programmable load capacitance the programmable lo ad capacitance has 16 values to suppor t crystal oscillators with a wide range of recommended load capacitance. if automatic load capacita nce stepping is enabled, the crystal load capacitors start at the smallest setting to allow a fast startup ti me, then slowly increase the capacitance until the final programmed value is reached. the final programmed loadin g capacitor value is specified using the loadcap bits in the rtc0xcf register. the loadcap setting specifies th e amount of on-chip load capacitance and does not include any stray pcb capacitance. once the final progr ammed loading capacitor valu e is reached, the loadrdy flag will be set by hardware to logic 1. when using the smartclock o scillator in self-osci llate mode, the programmable lo ad capacitance can be used to fine tune the oscillation frequency. in mo st cases, increasing the load capaci tor value will result in a decrease in oscillation frequency. .table 11.2 shows the crystal load capacitance for various settings of loadcap. table 11.2. smartclock load capacitance settings loadcap crystal load capacitance equivalent capacitance seen on xtal1 and xtal2 0000 4.0 pf 8.0 pf 0001 4.5 pf 9.0 pf 0010 5.0 pf 10.0 pf 0011 5.5 pf 11.0 pf 0100 6.0 pf 12.0 pf 0101 6.5 pf 13.0 pf 0110 7.0 pf 14.0 pf 0111 7.5 pf 15.0 pf 1000 8.0 pf 16.0 pf 1001 8.5 pf 17.0 pf 1010 9.0 pf 18.0 pf 1011 9.5 pf 19.0 pf 1100 10.5 pf 21.0 pf 1101 11.5 pf 23.0 pf 1110 12.5 pf 25.0 pf 1111 13.5pf 27.0pf www.datasheet.in
cp2400/1/2/3 76 rev. 1.0 11.2.4. automatic gain control and smartclock bias doubling automatic gain control allows the smartclock oscillator to trim the oscillation amplitude of a crystal in order to achieve the lowest possible power co nsumption. automatic gain control au tomatically detects when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it may be enabled during crystal startup. it is recommended to enable automatic gain co ntrol in any system which us es the smartclock oscillator in crystal mode. turning off automatic gain control will allow the crystal dr ive strength after oscillation is started to remain at the same level used for starting the crys tal. this will result in increased powe r consumption, however the crystal will have higher immunity against external factors. note: automatic gain control may be turned on in self-oscillate mode to reduce the oscillation frequency and the supply cur- rent. the smartclock bias doubling feature allows the self-osc illation frequency to be increased (almost doubled) and allows a higher crystal drive strength in crystal mode. high crystal drive strength is recommended when using a crystal with a high esr and high load ing capacitance. table 11.3 shows a summary of the os cillator operating modes and allowed opera ting conditions. smartclock bias doubling is enabled by settin g biasx2 (rtc0xcn.5) to 1. table 11.3. smartclock bias settings and allowed operating conditions mode setting power consumption allowed operating condition crystal bias double off, agc on lowest esr < 40 k ? , any load esr < 50 k ? , cload < 10 pf esr < 80 k ? , cload < 8 pf bias double off, agc off low esr < 80 k ? , cload < 10 pf bias double on, agc on high esr < 50 k ? , any load esr < 80 k ? , cload < 10 pf bias double on, agc off highest this mode is only recommended for debugging purposes due to its increased power consumption. self-oscillate bias double off low 20 khz bias double on high 40 khz www.datasheet.in
cp2400/1/2/3 rev. 1.0 77 11.2.5. missing smartclock detector the missing smartclock detector is a one-shot circuit enabled by setting mclken (rtc0cn.6) to 1. when the smartclock missing clock detector is enabled, oscf ail (rtc0cn.5) is set by hardware if smartclock oscillator remains high or low for more than 100 s. a smartclock missing clock detector timeout can trigger an interrupt and wake the device from a low power mode. see section ?7. interrupt sources? on page 40 and section ?9. power modes? on page 49, and for more information. note: the smartclock missing clock detector should be disabled when making changes to the oscillator settings in rtc0xcn. 11.2.6. smartclock oscillator crystal valid detector the smartclock oscillator crystal valid de tector is an oscillation amplitude detector circ uit used during crystal startup to determine when oscillation has started and is nearly stable. the output of this detector can be read from the clkvld bit (rtx0xcn.4). notes: the clkvld bit has a blanking interval of 2 ms. during the first 2 ms after turning on the crystal oscillator, the output of clkvld is not valid. this smartclock crystal valid detector (clkvld) is not intended for detecting an oscillator failure. the missing smartclock detector (clkfail) should be used for this purpose. 11.3. smartclock timer and alarm function the smartclock timer is a 32-bit counter that, when running (rtc0tr = 1), is incremented every smartclock oscillator cycle. the timer has an alarm function that can be set to generate an interrupt and wake the device from a low power mode. see section ?7. interrupt sources? on page 40 and section ?9. power modes? on page 49 more information. the smartclock timer includes an auto reset feature, which automatically resets the timer to zero one smartclock cycle after an alarm occurs. when using auto reset, the alarm match value should always be set to 1 count less than the desired match value. auto reset can be enabled by writing a 1 to alrm (rtc0cn.2). 11.3.1. setting and reading the smartclock timer value the 32-bit smartclock timer can be set or read using th e six capturen internal registers. note that the timer does not need to be stopped before reading or setting its value. the following steps can be used to set the timer value: 1. write the desired 32-bit set value to the capturen registers. 2. write 1 to rtc0set. this will transfer the conten ts of the capturen regi sters to the smartclock timer. 3. operation is complete when rtc0set is cleared to 0 by hardware. the following steps can be used to read the current timer value: 1. write 1 to rtc0cap. this will transfer the contents of the timer to th e capturen registers. 2. poll rtc0cap until it is cleared to 0 by hardware. 3. a snapshot of the timer value can be read from the capturen registers 11.3.2. setting a smartclock alarm the smartclock alarm function compares the 32-bit value of smartclock timer to the value of the alarmn registers. an alarm event is triggered if the smartclock timer is equal to the alarmn registers. if auto reset is enabled, the 32-bit timer will be cleared to zero one smartclo ck cycle after the alarm event. the smartclock alarm event can be configured to generate a wake-up from a low power mode, or generate an interrupt. see section ?7. interrupt sources? on page 40, section ?9. power modes? on page 49, and for more information. the following steps can be used to set up a smartclock alarm: www.datasheet.in
cp2400/1/2/3 78 rev. 1.0 1. disable smartclock alarm events (rtc0aen = 0). 2. set the alarmn registers to the desired value. 3. enable smartclock alar m events (rtc0aen = 1). notes: the alrm bit, which is used as the smartclock alarm event flag, is cleared by disabling smartclock alarm events (rtc0aen = 0). disabling (rtc0aen = 0) then re-enabling alarm events (rtc0aen = 1) after a smartclock alarm without modifying alarmn registers will automatically schedule the next al arm after 2^32 smartclock cycl es (approximately 36 hours using a 32.768 khz crystal). the smartclock alarm event flag will remain asserted for a maximum of one smartclock cycle. the alarm event however will be captured by th e interrupt logic and will po st a non-transient interrupt. 11.3.3. software considerations for using the smartclock timer and alarm the smartclock timer and alarm have two operating mo des to suit varying applications. the two modes are described below: mode 1 : the first mode uses the smartclock ti mer as a perpetual timebase which is never reset to zero. every 36 hours, the timer is allowed to overflow without being stopped or disrupted. the alarm interval is software managed and is added to the alrmn registers by software after each alarm. this allows the alarm match value to always stay ahead of the timer by one software managed interval. if so ftware uses 32-bit unsigned addition to increment the alarm match value, then it does not need to handle overflows since both the timer and the al arm match value will overflow in the same manner. this mode is ideal for applicat ions which have a long alarm interval (e.g., 24 or 36 hours) and/or have a need for a perpetual timebase. an example of an application that needs a perpetual ti mebase is one whose wake-up interval is constantly changing. for these applications, software ca n keep track of the number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year) perpetual timebase. mode 2 : the second mode uses the smartclock timer as a gener al purpose up counter which is auto reset to zero by hardware after each alarm. the alarm interval is ma naged by hardware and stored in the alrmn registers. software only needs to set the alarm interval once during device initialization. after each alarm, software should keep a count of the number of alarms that have occurred in order to keep track of time. this mode is ideal for applications th at require minimal software intervention and/or have a fixed alarm interval. this mode is the most power efficient si nce it requires less cpu time per alarm. www.datasheet.in
cp2400/1/2/3 rev. 1.0 79 smartclock address = 0x04 internal register definition 11 .4. rtc0cn: smartclock control bit76543210 name rtc0en mclken oscfail rtc0tr rtc0aen alrm rtc0set rtc0cap type r/w r/w r/w r/w r/w r/w r/w r/w reset 00varies00000 bit name function 7rtc0en smartclock enable. enables/disables the smartclock osc illator and associat ed bias currents. 0: smartclock oscillator disabled. 1: smartclock oscillator enabled. 6mclken missing smartclock detector enable. enables/disables the missing smartclock detector. 0: missing smartclock detector disabled. 1: missing smartclock detector enabled. 5oscfail smartclock oscillato r fail event flag. set by hardware when a missing smartclock dete ctor timeout occurs. must be cleared by software. the value of this bit is not defined when the smartclock oscillator is disabled. 4rtc0tr smartclock timer run control. controls if the smartclock timer is running or stopped (holds current value). 0: smartclock timer is stopped. 1: smartclock timer is running. 3 rtc0aen smartclock alarm enable. enables/disables the smartclock alarm function. also clears the alrm flag. 0: smartclock alarm disabled. 1: smartclock alarm enabled. 2alrm smartclock alarm event flag and auto reset enable reads return the state of the alarm event flag. writes enable/disable the auto reset function. read: 0: smartclock alarm event flag is de-asserted. 1: smartclock alarm event flag is asserted. write: 0: disable auto reset. 1: enable auto reset. 1 rtc0set smartclock timer set. writing 1 initiates a smartclock ti mer set operation. this bit is cleared to 0 by hardware to indicate that the timer set operation is complete. 0rtc0cap smartclock timer capture. writing 1 initiates a smartclock timer capture oper ation. this bit is cleared to 0 by hardware to indicate that the timer capture operation is complete. note: the alrm flag will remain asserted for a maximum of one smartclock cycle. www.datasheet.in
cp2400/1/2/3 80 rev. 1.0 smartclock address = 0x05 internal register definition 11.5. rtc 0xcn: smartclock os cillator control bit76543210 name agcen xmode biasx2 clkvld type r/wr/wr/wrrrrr reset 00000000 bit name function 7agcen smartclock oscillator automati c gain control (agc) enable. 0: agc disabled. 1: agc enabled. 6xmode smartclock oscillator mode. selects crystal or self oscillate mode. 0: self-oscillate mode selected. 1: crystal mode selected. 5 biasx2 smartclock oscillator bias double enable. enables/disables the bias double feature. 0: bias double disabled. 1: bias double enabled. 4 clkvld smartclock oscillator crystal valid indicator. indicates if oscillation amplitude is su fficient for maintaining oscillation. 0: oscillation has not started or oscillation amplitude is too low to maintain oscillation. 1: sufficient oscillati on amplitude detected. 3:0 unused read = 0000b; write = don?t care. www.datasheet.in
cp2400/1/2/3 rev. 1.0 81 smartclock address = 0x06 internal register definition 11.6. rtc0x cf: smartclock oscillator configuration bit7 6 5 4 3210 name autostp loadrdy loadcap type r/w r r r r/w reset 0 0 0 0 0000 bit name function 7autostp automatic load capacitance stepping enable. enables/disables automatic load capacitance stepping. 0: load capacitance stepping disabled. 1: load capacitance stepping enabled. 6 loadrdy load capacitance ready indicator. set by hardware when the load capa citance matches the programmed value. 0: load capacitance is currently stepping. 1: load capacitance has reached it programmed value. 5:4 unused read = 00b; write = don?t care. 3:0 loadcap load capacitance programmed value. holds the user?s desired value of the load capacitance. see table 11.2 on page 75. www.datasheet.in
cp2400/1/2/3 82 rev. 1.0 smartclock addresscapture0 = 0x00; capture1 = 0x01; capture2 =0x02; capture3: 0x03. smartclock addressalarm0 = 0x08; alarm1 = 0x09; alarm2 = 0x0a; alarm3 = 0x0b internal register definition 11.7. c apturen: smartclock timer capture bit76543210 name capture[31:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 capture[31:0] smartclock timer capture. these 4 registers (capture3?capture0) are used to read or set the 32-bit smart- clock timer. data is transferred to or from the smartclock timer when the rtc0set or rtc0cap bits are set. note: the least significant bit of the timer capture value is in capture0.0. internal register definition 11.8. al armn: smartclock alar m programmed value bit76543210 name alarm[31:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 alarm[31:0] smartclock alarm programmed value. these 4 registers (alarm3?alarm0) are used to set an alarm event for the smartclock timer. the smartclock alarm should be dis abled (rtc0aen=0) when updating these reg- isters. note: the least significant bit of the alarm programmed value is in alarm0.0. www.datasheet.in
cp2400/1/2/3 rev. 1.0 83 12. lcd segment driver cp2400/1/2/3 devices contain an lcd segm ent driver and on-chip bias generation that supports static, 2-mux, 3- mux and 4-mux lcds with 1/2 or 1/3 bias. the on-chi p charge pump with programmable output voltage allows software contrast control which is independent of the vdd supply voltage. lcd timing is derived from the smartclock oscillator to allo w precise control over the refresh rate. a low frequency clock present on the clk pin may also be used as the lcd clock source. the cp2400/1/2/3 contains on-chip ulp memory to store the enabled/disabled state of individual lcd segments. all lcd waveforms are generated on-chip and software only needs to access the ulp memory to change the information displayed on the lcd. an lcd blinking functi on is also supported. a block diagram of the lcd segment driver is shown in figure 12.1. figure 12.1. lcd segment driver block diagram 12.1. initializing the lcd segment driver the following procedure is recommended for using the lcd segment driver: 1. configure the lcd size, mux mode, and bias using the lcd0cn register. 2. configure the port i/o pins to be used for lcd as analog i/o. 3. set the lcd contrast using the contrast register. 4. write the reserved value of 0x9f to lcd0cf. 5. set the lcd refresh rate using the lcd0divh:lcd0divl registers. 6. set the lcd toggle rate using the lcd0togr register. 7. set the lcd power mode using the lcd0pwr register. 8. write a pattern to the ulp memory. 9. enable the lcd using the master control (mscn) register. lcd segment driver vdd charge pump cap 10 uf bias generator ulp memory port drivers segment pins 4 com pins lcd state machine configuration registers cpbyp smartclock clk xtal1 xtal2 rtcbyp www.datasheet.in
cp2400/1/2/3 84 rev. 1.0 12.2. lcd configuration the lcd segment driver supports multiple mux options: st atic, 2-mux, 3-mux, and 4-mux mode. it also supports 1/2 and 1/3 bias options. the desired mux mode and bi as is configured through the lcd0cn register. address = 0x95 sfr definition 12.1. lcd0cn: lcd0 control register bit76543210 name blank size muxmd bias type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 unused read = 000. write = don?t care. 4 blank blank all segments. blanks all lcd segments using a single bit. 0: all lcd segments are controlled by the lcd memory. 1: all lcd segments are blank (turned off). 3 size lcd size select. selects whether 16 or 32 segment pi ns will be used for the lcd function. 0: p0 and p1 are used as lcd segment pins. 1: p0, p1, p2, and p3 are used as lcd segment pins. 2:1 muxmd[1:0] lcd bias power mode. selects the mux mode. 00: static mode selected. 01: 2-mux mode selected. 10: 3-mux mode selected. 11: 4-mux mode selected. 0 bias bias select . selects between 1/2 bias and 1/3 bias. 0: lcd0 is configured for 1/3 bias. 1: lcd0 is configured for 1/2 bias. www.datasheet.in
cp2400/1/2/3 rev. 1.0 85 12.3. lcd bias generation a nd contrast adjustment the lcd bias voltages are generated using the on-chi p charge pump with programmable output voltage. the programmable output voltage allows software contrast cont rol in 60 mv steps from 2.6 to 3.44 v. the lcd contrast is controlled by the contrast register. note: an external 4.7 f decoupling capacitor is required (10 f recommended) on the cap pin to create a charge reservoir at the output of the charge pump. intermediate voltages used for 1/2 and 3/4 bias configur ations are generated on-chip using a novel approach that allows driving extra large l cd segments while maintaining ultra low power consumption. this eliminates the need for off-chip biasing when dr iving a large lcd. the lcd drive capabilit y can be set using the lcd0pwr register. the highest power setting should be used for extra lar ge lcds (which require charging the largest capacitance) and the lowest power setting should be used with small lcds (smaller than 1 inch). address = 0x96 sfr definition 12.2. contras t: contrast adjustment bit76543210 name cntrst type r/w r/w r/w r/w r/w reset 00000000 bit name function 7:4 unused read = 0000. write = don?t care. 3:0 cntrst contrast adjustment. selects the on-chip charge pump output voltage. 0000: 2.60 v 0001: 2.60 v 0010: 2.66 v 0011: 2.72 v 0100: 2.78 v 0101: 2.84 v 0110: 2.90 v 0111: 2.96 v 1000: 3.02 v 1001: 3.08 v 1010: 3.14 v 1011: 3.20 v 1100: 3.26 v 1101: 3.32 v 1110: 3.38 v 1111: 3.44 v www.datasheet.in
cp2400/1/2/3 86 rev. 1.0 address = 0x97 sfr definition 12.3. lcd0cf: lcd configuration bit76543210 name reserved cpcyc[5:0] type r/w r/w reset 10011111 bit name function 7:4 reserved read = 10b. must write 10b. 5:0 cpcyc[5:0] charge pump cycle period. the number of smartclock oscillator periods between charge pump cycles is cpcyc[5:0]+1. the time between charge pump cycles should not exceed 2 ms. www.datasheet.in
cp2400/1/2/3 rev. 1.0 87 12.4. lcd timing generation all lcd timing is derived from the smartclock oscillator divided by 2. the lcd0divh:lcd0divl registers store the prescaler for generating the lcd refresh rate. the lcd mux mode must be taken into account when determining the prescaler value. see the lcd0divh/lcd0divl register descriptions for more details. for maximum power savings, choose a slow lcd refresh rate. for the least flicker, choose a fast lcd refresh rate. address = 0x98 address = 0x99 sfr definition 12.4. lcd0divh: lcd refresh rate prescaler high byte bit76543210 name lcd0div[9:8] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:2 unused read = 000000. write = don?t care. 1:0 lcd0div[9:8] lcd refresh rate prescaler . sets the lcd refresh rate according to the following equation: sfr definition 12.5. lcd0divl: lcd refresh rate prescaler low byte bit76543210 name lcd0div[7:0] type r/w reset 00000000 bit name function 7:0 lcd0div[7:0] lcd refresh rate prescaler . sets the lcd refresh rate according to the following equation: lcd refresh rate smartclock oscillator frequency 4 mux_mode ? lcd0div 1 + ?? ? ------------------------------------------------------------------------------------------- - = lcd refresh rate smartclock oscillator frequency 4 mux_mode ? lcd0div 1 + ?? ? ------------------------------------------------------------------------------------------- - = www.datasheet.in
cp2400/1/2/3 88 rev. 1.0 address = 0x9a sfr definition 12.6. lcd0togr: lcd toggle rate bit76543210 name togr[3:0] type r/wr/wr/wr/w r/w reset 00000000 bit name function 7:4 unused read = 0000. write = don?t care. 3:0 togr[3:0] lcd toggle rate divider . sets the lcd toggle rate according to the following equation: 0000: reserved. 0001: reserved. 0010: toggle rate divider is set to divide by 2. 0011: toggle rate divider is set to divide by 4. 0100: toggle rate divider is set to divide by 8. 0101: toggle rate divider is set to divide by 16. 0110: toggle rate divider is set to divide by 32. 0111: toggle rate divider is set to divide by 64. 1000: toggle rate divider is set to divide by 128. 1001: toggle rate divider is set to divide by 256. 1010: toggle rate divider is set to divide by 512. 1011: toggle rate divider is set to divide by 1024. 1100: toggle rate divider is set to divide by 2048. 1101: toggle rate divider is set to divide by 4096. all other values reserved. lcd toggle rate refresh rate mux_mode 2 ? ? toggle rate divider -------------------------------------------------------------------------------- - = www.datasheet.in
cp2400/1/2/3 rev. 1.0 89 address = 0x9b sfr definition 12.7. lcd0pwr: lcd0 power register bit76543210 name cpclk[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 reserved read = 000b. must write 000b. 4:3 cpclk[1:0] charge pump clock select. 00: 1 mhz charge pump clock (normal operation). 01: 2 mhz charge pump clock. 10: 0.5 mhz charge pump clock. 11: 0.67 mhz charge pump clock. 2:0 reserved read = 000b. must write 000b. www.datasheet.in
cp2400/1/2/3 90 rev. 1.0 12.5. mapping ulp memory to lcd pins the ulp memory is organized in 16 bytes (32 half-bytes or nibbles), ea ch nibble controlling 1 lcd output pin. each lcd output pin can control 1 to 4 lcd segments dep ending on the selected mux mode. the least significant bit of each nibble controls the segmen t connected to the backplane signal com0 and the most significant bit of each nibble controls the segment c onnected to the backplane signal com3 . in static mode, only com0 is used and the three remaining bits in each nibble are ignore d. in 4-mux mode, each bit controls an lcd segment. bits with a value of 1 turn on the associated segment and bits with a value of 0 turn off the associated segment. figure 12.2. ulp memory map ulpmem15 (pins: lcd31, lcd30) ulpmem14 (pins: lcd29, lcd28) ulpmem13 (pins: lcd27, lcd26) ulpmem12 (pins: lcd25, lcd24) ulpmem11 (pins: lcd23, lcd22) ulpmem10 (pins: lcd21, lcd20) ulpmem09 (pins: lcd19, lcd18) ulpmem08 (pins: lcd17, lcd16) ulpmem07 (pins: lcd15, lcd14) ulpmem06 (pins: lcd13, lcd12) ulpmem05 (pins: lcd11, lcd10) ulpmem04 (pins: lcd9, lcd8) ulpmem03 (pins: lcd7, lcd6) ulpmem02 (pins: lcd5, lcd4) ulpmem01 (pins: lcd3, lcd2) ulpmem00 (pins: lcd1, lcd0) com0 com1 com2 com3 com0 com1 com2 com3 0 1 2 3 4 5 6 7 bit: www.datasheet.in
cp2400/1/2/3 rev. 1.0 91 12.6. blinking lcd segments the lcd driver supports blinking lcd applications such as clock applications where the ?colon? separator toggles on and off once per second. if the lcd is only displa ying the hours and minutes, then the device only needs to wake up once per minute to update the display. the once per second blinking is automatically handled by the cp2400/1/2/3. the lcd0blink register can be used to enable blinking on any lcd segment connected to the lcd0 or lcd1 segment pin. in static mode, a maximum of 2 segments can blink. in 4-mux mode, a maximum of 8 segments can blink. the lcd0blink mask register targets the same lcd segments as the ulpmem00 register. if an lcd0blink bit corresponding to an lcd segment is set to 1, then that segment will toggle at the frequency set by the lcd0togr register without any software intervention. address = 0x80 sfr definition 12.8. lcd0bl ink: lcd0 blink mask bit76543210 name lcd0blink[7:0] type r/wr/wr/wr/wr/wr/wr/wr/w reset 00000000 bit name function 7:0 lcd0blink[7:0] lcd0 blink mask. each bit maps to a specific lcd segment connected to the lcd0 and lcd1 segment pins. a value of 1 indicates that the segment is blinking. a value of 0 indicates that the segment is not blinking. this bit to segm ent mapping is the sa me as the ulpmem00 register. www.datasheet.in
cp2400/1/2/3 92 rev. 1.0 13. timers cp2400/1/2/3 devices include two 16-bit auto-reload timers. these timers c an be used to measure time intervals and generate periodic interrupt requests. both timers can be clocked from the system clock source divided by 12. timer 1 has an additional smartclock divided by 8 in put and capture mode that can be used to measure the smartclock oscillation frequency with respect to the system clock. when smbus scl low timeout is enabled, timer 0 becomes unavailable for general pu rpose use. timer 0 is enabled on reset. 13.1. timer 0 timer 0 is a 16-bit timer formed by two 8-bit sfrs: tmr0 l (low byte) and tmr0h (high byte). timer 0 operates in 16-bit auto-reload mode and is clocked by the system cl ock divided by 12. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 0 reload registers (tmr0rlh and tmr0rll) is loaded into the timer 0 register as shown in figure 13.1, and the timer 0 overflow flag (int1.2) is set. if timer 0 interrupts are enabled (if int1 en.2 is set), an interrupt will be generated on each timer 0 overflow. additionally, if timer 0 interrupts are enabled and the tf0len bit is set (tmr 0cn.5), an interrup t will be generated each time the lower 8 bits (tmr0l) overflow from 0xff to 0x00. figure 13.1. timer 0 block diagram sysclk / 12 tmr0l tmr0h tmr0rll tmr0rlh reload tr0 to smbus low byte overflow to interrupt www.datasheet.in
cp2400/1/2/3 rev. 1.0 93 sfr address = 0x54 sfr definition 13.1. tmr 0cn: timer 0 control bit76543210 name tf0len tr0 type r/wr/wr/wr/wr/wr/wr/wr/w reset 00000100 bit name function 7:6 unused read = 00b. write = don?t care. 5 tf0len timer 0 low byte interrupt enable. when set to 1, this bit enables timer 0 low byte interrupts. if timer 0 interrupts are enabled, an interrupt will be generated when the low byte of timer 0 overflows. 4:3 unused read = 00b. write = don?t care. 2tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 1:0 unused read = 00b. write = don?t care. www.datasheet.in
cp2400/1/2/3 94 rev. 1.0 sfr address = 0x50 sfr address = 0x51 sfr definition 13.2. tmr0rll: time r 0 reload register low byte bit76543210 name tmr0rll[7:0] type r/w reset 10001101 bit name function 7:0 tmr0rll[7:0] timer 0 reload register low byte. tmr0rll holds the low byte of the reload value for timer 0. sfr definition 13.3. tmr0rlh: time r 0 reload register high byte bit76543210 name tmr0rlh[7:0] type r/w reset 00110100 bit name function 7:0 tmr0rlh[7:0] timer 0 reload register high byte. tmr0rlh holds the high byte of the reload value for timer 0. www.datasheet.in
cp2400/1/2/3 rev. 1.0 95 sfr address = 0x52 sfr address = 0x53 sfr definition 13.4. tmr0l: timer 0 low byte bit76543210 name tmr0l[7:0] type r/w reset 00000000 bit name function 7:0 tmr0l[7:0] timer 0 low byte. contains the low byte of the 16-bit timer 0. sfr definition 13.5. tmr 0h timer 0 high byte bit76543210 name tmr0h[7:0] type r/w reset 00000000 bit name function 7:0 tmr0h[7:0] timer 0 high byte. contains the high byte of the 16-bit timer 0. www.datasheet.in
cp2400/1/2/3 96 rev. 1.0 13.2. timer 1 timer 1 is a 16-bit timer formed by two 8-bit sfrs: tmr1 l (low byte) and tmr1h (high byte). timer 1 operates in 16-bit auto-reload mode and is clocked by the system cl ock divided by 12 or smartclock divided by 8. as the 16- bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 1 reload registers (tmr1rlh and tmr1rll) is loaded into the timer 1 regi ster as shown in figure 13.1, and the timer 1 overflow flag (int1.3) is set. if timer 1 interrupts are enabled (if in1en.3 is set), an interrupt will be generated on each timer 1 overflow. additionally, if timer 1 interrupts are enabled and the tf0len bit is set (tmr0cn.5), an interrupt will be generated each time the lower 8 bits (tmr0l) over flow from 0xff to 0x00. figure 13.2. timer 1 block diagram sysclk / 12 smartclock / 8 tmr1l tmr1h tmr1rll tmr1rlh reload tr1 to cs0 low byte overflow to interrupt 0 1 t1xclk www.datasheet.in
cp2400/1/2/3 rev. 1.0 97 13.2.1. timer 1 smartclock oscillator capture mode the capture mode in timer 1 allows the smartclock oscilla tor period to be measured against the system clock d by 12. setting tf1cen to 1 enables the smartclock oscilla tor capture mode for timer 1. when capture mode is enabl ed, a capture event will be generated ever y 8 smartclock oscillator cycles. when the capture event occurs, the contents of timer 1 (tmr1h :tmr1l) are loaded into the timer 1 reload registers (tmr3rlh:tmr3rll) and the t1f interrupt flag is set (triggering an interrupt if timer 1 interrupts are enabled). by recording the difference between two successive timer capture values, the smartclock period can be determined with respect to the system clock divided by 12. the system clock divided by 12 should be much faster than the smartclock to achieve an accurate reading. for example, if t1xclk = 0b, and tf1cen = 1b, timer 1 w ill increment every 12 system clock cycles and capture every 8 smartclock cycles. if the system clock is 24.5 mhz and the smartclock is 32.768 khz, the difference between two successive captur es should be approximatel y 498 counts. knowing the system clock frequency, the smartclock frequency can be estimated as: (sysclk x 8 / 12) / counts = (24500000 hz x 8 / 12) / 498 = 16333333 / 498 = 32797 hz. this mode allows software to dete rmine the smartclock osc illator frequency when th e smartclock oscillator is being used in self-oscillate mode without a crystal. figure 13.3. timer 1 capture mode block diagram smartclock / 8 sysclk / 12 tmr1l tmr1h tclk tr1 tmr1rll tmr1rlh capture tf1cen interrupt www.datasheet.in
cp2400/1/2/3 98 rev. 1.0 sfr address = 0x59 sfr definition 13.6. tmr 1cn: timer 1 control bit76543210 name tf1len tf1cen tr1 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:6 unused read = 00b. write = don?t care. 5 tf1len timer 1 low byte interrupt enable. when set to 1, this bit enables timer 1 low byte interrupts. if timer 1 interrupts are enabled, an interrupt will be generated when the low byte of timer 1 overflows. 4tf1cen timer 1 smartclock oscillator capture enable. when set to 1, this bit enables the timer 1 smartclock os cillator c apture mode. 3 unused read = 00b. write = don?t care. 2tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 1 unused read = 0b. write = don?t care. 0t1xclk timer 1 external clock select. 0: timer 1 is clocked from the system clock divided by 12. 1: timer 1 is clocked from the sm artclock oscillator divided by 8. www.datasheet.in
cp2400/1/2/3 rev. 1.0 99 sfr address = 0x55 sfr address = 0x56 sfr definition 13.7. tmr1rll: time r 1 reload register low byte bit76543210 name tmr1rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr1rll[7:0] timer 1 reload register low byte. tmr1rll holds the low byte of the reload value for timer 1. sfr definition 13.8. tmr1rlh: time r 1 reload register high byte bit76543210 name tmr1rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr1rlh[7:0] timer 1 reload register high byte. tmr1rlh holds the high byte of the reload value for timer 1. www.datasheet.in
cp2400/1/2/3 100 rev. 1.0 sfr address = 0x57 sfr address = 0x58 sfr definition 13.9. tmr1l: timer 1 low byte bit76543210 name tmr1l[7:0] type r/w reset 00000000 bit name function 7:0 tmr1l[7:0] timer 1 low byte. contains the low byte of the 16-bit timer 1. sfr definition 13.10. tmr1h timer 1 high byte bit76543210 name tmr1h[7:0] type r/w reset 00000000 bit name function 7:0 tmr1h[7:0] timer 1 high byte. contains the high byte of the 16-bit timer 1. www.datasheet.in
cp2400/1/2/3 rev. 1.0 101 14. serial peripheral interface (spi) cp2400/2 devices have a 4-wire serial peripheral interface which provides access to the internal registers and memory. a typical connection to a spi master is shown in figure 14.1. figure 14.1. spi connection diagram 14.1. signal descriptions the four signals used by the spi (mosi, miso, sck, nss) are described below. 14.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output from a master device and an input to slave devices. it is used to serially transfer data from the master to the slave. th is signal is always in input for CP2402/1 devices. data is transferred most-signi ficant bit first. 14.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the mast er. this signal is always an output for CP2402/1 devices. data is transferred most-significant bit first. the miso pin is placed in a high-impedance state when the slave select (nss) signal is de-asserted. 14.1.3. serial clock (sck) the serial clock (sck) signal is an output from the ma ster device and an input to slave devices. it is used to synchronize the transfer of data between the master and slave on the mosi and miso lines. this signal is always an input for CP2402/1 devices. the sck signal is ignor ed when the slave select (nss) signal is de-asserted. 14.1.4. slave select (nss) the active-low slave-select (nss) signal allows support for multiple slave devices on a single bus. it is also used by the CP2402/1 to detect the st art and end of a spi transfer. slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss int gpio gpio int www.datasheet.in
cp2400/1/2/3 102 rev. 1.0 14.2. serial clock timing the clock to data relationship is shown in figure 14.2. if the spi master is a c8051 microcontroller, its spi peripheral must be configured for mode 0 communication (ckpol = 0, ckpha = 0). the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the syst em clock frequency, provided that the master issues sck, nss, and the serial input data synchronously with the system clock. if the master issues sck, nss, and the serial input data asynchronously , the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the device and does not need to receive data back (i.e. ha lf-duplex operation), the slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master issues sck, nss, and the serial input data synchronously with the system clock. figure 14.2. data/clock timing msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) www.datasheet.in
cp2400/1/2/3 rev. 1.0 103 figure 14.3. spi slave timing table 14.1. spi slave timing parameters parameter description min max units t se nss falling to first sck edge 2 x t sysclk ?ns t sd last sck edge to nss rising 2 x t sysclk ?ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ?ns t ckl sck low time 5 x t sysclk ?ns t sis mosi valid to sck sample edge 2 x t sysclk ?ns t sih sck sample edge to mosi change 2 x t sysclk ?ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6xt sysclk 8xt sysclk ns note: t sysclk is equal to one period of the device system clock (sysclk). sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh t sez t sdz www.datasheet.in
cp2400/1/2/3 104 rev. 1.0 15. smbus interface the smbus i/o interface is a two-wire, bi-directional serial bus that can be used to access the internal registers and memory on cp2401/3 devices. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i2c serial bus. reads an d writes to the interface by the system controller are byte oriented with the sm bus interface autonomously controlling the serial transfe r of the data. data can be transferred at up to 1/20th of the system clock (thi s can be faster than allowed by the smbus specification, depending on the system clock used). a me thod of extending the clock-low du ration is available to accommodate devices with different speed capabilities on the same bus. 15.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including specifications), ph ilips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification? version 1.1, sbs implementers forum. 15.2. smbus configuration figure 15.1 shows a typical smbus configuration. the sm bus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-directional scl (serial clock) and sda (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. every device connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessi ve state) when the bus is free. the maximum number of devices on the bus is limited only by t he requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 15.1. typical smbus configuration vdd = 5 v master device slave device 1 slave device 2 vdd = 3 v vdd = 5 v vdd = 3 v sda scl www.datasheet.in
cp2400/1/2/3 rev. 1.0 105 15.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addressed slave tr ansmitter to a master receiver (read). the master device initiates both types of data transfers and provides the se rial clock pulses on scl. the smbus interface on cp2401/ 3 devices only supports slave receiver and slave transmitter modes. a typical smbus transaction consists of a start condit ion followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of dat a, and a stop condition. bytes that are received (by a master or slave) are acknowledged (ack) with a low sda during a high scl (see figure 15.2). if the receiving device does not ack, the transmitting device will read a nack (not acknowledge), wh ich is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit posi tion of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or mo re addressed slave devices as the target. the master generates the start condition and then transmits the sl ave address and direction bit. if the transaction is a write operation from the master to the slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operat ions, the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transactio n and free the bus. figure 15.2 illust rates a typical sm bus transaction. figure 15.2. smbus transaction 15.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an address or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is sent by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, during which ti me the receiver controls the sda line. 15.3.2. clock low extension smbus provides a clock synchroniz ation mechanism, similar to i 2 c, which allows devices with different speed capabilities to coexist on th e bus. a clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. the slave ma y temporarily hold the scl line low to extend the clock low period, effectively decreasin g the serial clock frequency. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop www.datasheet.in
cp2400/1/2/3 106 rev. 1.0 15.3.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct the erro r condition. to solve this problem, the smbus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a ?timeout? condition. devices that have detected the time out condition must reset the communication no later than 10 ms after detecting the timeout condition. when smbus is used for communication with the host microcontroller, timer 0 is used to detect scl low timeouts. timer 0 is forced to reload when scl is high, and allowe d to count when scl is low. with timer 0 enabled and configured to overflow after 25 ms, the timer 0 interr upt service routine can be used to alert the host microcontroller of an scl low timeout. after an scl low timeout, th e smbus slave will reset its internal state machine and will be ready to respond to new transfers. on reset or wake-up from ulp mode, timer 0 is enabled and configured for scl low timeout detection. the scl low timeout may be disabled by clearing the smbtoe bit in the smb0cf register. this allo ws full software control of timer 0. 15.3.4. scl high (smbus free) timeout the smbus specification stipul ates that if the scl and sda lines rema in high for more that 50 s, the bus is designated as free. when the smbfte bit in smb0cf is set, the bus will be considered free if scl and sda remain high for more t han 1250 system clock period s. after an scl high timeout, the smbus slave will reset its internal state machine and will be ready to re spond to new transfers. 15.3.5. slave address selection cp2400/1/2/3 devices can have one of 2 possible 7-bit, left-justified sl ave addresses: 0x74 and 0x76. the least significant bit of the slave address is set by the smba0 pi n. the remaining bits in the slave address are fixed. the bit following the least significant address bit is used to indicate whether the current transfer is a read or a write. www.datasheet.in
cp2400/1/2/3 rev. 1.0 107 address: 0x68 sfr definition 15.1. smbcf: smbus clock/configuration bit 76543210 name ensmb inh busy exthold smbtoe smbfte reserved type r/w r/w r r/w r/w r/w r/w reset (cp2400/2) 00000000 reset (cp2401/3) 10011100 bit name function 7ensmb smbus enable. this bit enables the smbus interface when set to 1. when enabled, the interface constantly monitors the sda and scl pins. 6inh smbus slave inhibit. when this bit is set to logic 1, the smbus does not generate an interrupt when slave events occur. this effectively remove s the smbus slave from the bus. 5busy smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold smbus setup and hold time extension enable. this bit controls the sda setup and hold times. 0: setup time is 4 system clocks and hold time is 3 system clocks. 1: setup time is 11 system clocks an d hold time is 12 system clocks. 3smbtoe smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 0 to reload while scl is high and allows timer 0 to count when scl goes low. the timer 0 reload value should be set to overflow the timer after 25 ms. 2smbfte smbus free timeout detection enable. when this bit is set to logic 1 , the bus will be consider ed free if scl and sda remain high for more than 50 s. 1 :0 reserved read = 00b. must write 00b. note: this register has a reset value of 0x00 in devices that do not support smbus. www.datasheet.in
cp2400/1/2/3 108 rev. 1.0 d ocument c hange l ist revision 0.2 to revision 1.0 ? updated electrical specificat ions to remove tbds and specify min/max parameters. ? updated reset values for various registers. ? updated register description for lcd0pwr register. www.datasheet.in
cp2400/1/2/3 rev. 1.0 109 n otes : www.datasheet.in
cp2400/1/2/3 110 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and usbxpre ss are trademarks of silicon laboratories inc. intel, motorola, and any other products or brandnames mentioned herein are trademarks or register ed trademarks of their respect ive holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsi bility for any consequences resu lting from the use of information included herein. additionally, silicon laborator ies assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no war- ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon labor atories assume any liability arising out of the application or use of any pr oduct or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages . silicon laboratories products are not de signed, intended, or authorized for use in appli- cations intended to support or sustain life, or for any other appl ication in which the failure of the silicon laboratories prod uct could create a situation where personal injury or death may occur. should bu yer purchase or use silicon laboratories products for any such u nintended or unauthorized application, buyer sha ll indemnify and hold silicon laboratories harmless against all claims and damages. www.datasheet.in

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